career-path—business-intelligence-analyst By Uplatz<\/a><\/h3>\nThe integration of NPUs into the heterogeneous System-on-Chip (SoC) of smartphones, laptops, and Internet of Things (IoT) devices is enabling a new generation of on-device AI experiences. These range from enhancing existing features, such as computational photography and real-time video effects, to enabling entirely new capabilities like offline language translation and proactive, OS-level AI assistants. Critically, by performing these tasks locally, the NPU provides a foundational layer of privacy and security, as sensitive user data does not need to be transmitted to the cloud.<\/span><\/p>\nHowever, the NPU ecosystem faces significant challenges, most notably a fragmented software landscape with vendor-specific APIs and development toolchains. The industry’s convergence on standards like the ONNX model format is crucial to mitigating this complexity for developers. Looking forward, the evolution of NPU technology will be defined by advancements in memory hierarchies, interconnect technologies like photonics, and a gradual blurring of the lines between NPUs and GPUs as both architectures evolve to balance fixed-function efficiency with programmable flexibility. The NPU is not merely an incremental hardware update; it is the core enabler of a more personal, private, and pervasive AI-integrated future.<\/span><\/p>\n <\/p>\n
Section 1: The New Brain of the Machine: Defining the Neural Processing Unit<\/b><\/h2>\n
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The emergence of the Neural Processing Unit (NPU) represents a pivotal moment in the evolution of computing architecture, marking a deliberate shift from general-purpose processing toward specialized hardware designed to meet the unique and voracious computational demands of artificial intelligence. This section defines the NPU, contextualizes its development, and establishes its primary role as the engine for AI inference at the network’s edge.<\/span><\/p>\n <\/p>\n
1.1 The Computational Imperative: From General-Purpose to Specialized Acceleration<\/b><\/h3>\n
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For decades, the CPU has served as the versatile heart of computing systems, while the GPU later emerged to handle the parallelizable workloads of graphics rendering. However, as AI models grew in complexity, it became clear that these traditional architectures were struggling to keep pace with the demand for greater speed and energy efficiency.<\/span>1<\/span> The history of computing is marked by a consistent trend toward offloading specific, intensive workloads to dedicated co-processors. The floating-point unit (FPU) for scientific computing and the digital signal processor (DSP) for audio processing are historical precedents for this architectural specialization.<\/span>2<\/span> The NPU is the logical and necessary next step in this evolutionary path, a processor designed from the ground up to address the specific computational patterns of AI and machine learning.<\/span>2<\/span> This architectural divergence is not an incremental improvement but a response to the exponential growth in AI’s prevalence and complexity, which demanded a new class of hardware.<\/span><\/p>\n <\/p>\n
1.2 The NPU Paradigm: Architecture and Core Purpose<\/b><\/h3>\n
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An NPU is a specialized hardware accelerator, also referred to as an AI accelerator or deep learning processor, engineered to drastically speed up AI and machine learning applications, including artificial neural networks and computer vision.<\/span>4<\/span> Its fundamental design principle is to mimic the structure and efficiency of biological neural networks at the silicon level, creating an architecture optimized for the mathematical operations that underpin modern AI.<\/span>1<\/span> This is achieved through what is described as a “data-driven parallel computing” architecture, which is exceptionally proficient at processing the massive multimedia data streams common in AI tasks.<\/span>8<\/span><\/p>\nThe core function of an NPU is to execute the fundamental mathematics of neural networks\u2014primarily vast quantities of matrix multiplication, convolution, and addition operations\u2014with a level of efficiency that general-purpose processors cannot match.<\/span>1<\/span> While a CPU might require thousands of instructions to process the operations of a single virtual neuron, an NPU can accomplish this with a single instruction from a deep learning instruction set, vastly improving operational efficiency.<\/span>8<\/span><\/p>\nBeyond its technical definition, the “NPU” concept also serves as a powerful marketing vehicle. The deliberate analogy to the “human brain” <\/span>6<\/span> is a strategic abstraction. While not a literal representation of the hardware’s function, this framing translates the complex reality of tensor math into a tangible and desirable concept for the mass market: an “intelligent” device. This narrative shifts consumer focus from traditional metrics like clock speed to the novel capabilities enabled by on-device AI, such as a phone that “knows what you want before you even ask”.<\/span>10<\/span> The market success of the “AI PC” and next-generation smartphones thus depends as much on the effective communication of this intelligence narrative as on the underlying hardware’s performance.<\/span><\/p>\n <\/p>\n
1.3 Inference at the Edge: The NPU’s Primary Domain<\/b><\/h3>\n
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To understand the NPU’s role in consumer devices, it is essential to distinguish between the two primary phases of an AI model’s lifecycle: <\/span>training<\/span><\/i> and <\/span>inference<\/span><\/i>. Training involves teaching a model by processing massive datasets, a computationally immense task typically performed in data centers on clusters of powerful, high-precision GPUs.<\/span>5<\/span> Inference, in contrast, is the process of using an already trained model to make predictions or decisions based on new, real-world data.<\/span>5<\/span><\/p>\nThe NPU’s domain is almost exclusively inference, executed locally on the device\u2014a paradigm known as “edge computing” or “AI at the edge”.<\/span>3<\/span> Consumer devices are designed to run smaller, highly optimized models that can perform specific tasks quickly and efficiently without needing to communicate with a remote server.<\/span>5<\/span> This focus on efficient inference is the guiding principle behind the NPU’s entire design philosophy. It is not built for the brute-force flexibility and high-precision calculations required for training but for the lightning-fast, power-sipping execution of the specific, repetitive tasks that define modern on-device AI experiences.<\/span><\/p>\n <\/p>\n
Section 2: A Heterogeneous World: Architectural Comparison of Processing Units<\/b><\/h2>\n
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Modern consumer devices rely on a sophisticated interplay of multiple specialized processors integrated onto a single piece of silicon. This “heterogeneous computing” model is essential for balancing performance, versatility, and power efficiency. To fully appreciate the NPU’s contribution, it is necessary to compare its architecture and function against its counterparts: the CPU and the GPU.<\/span><\/p>\n <\/p>\n
2.1 The CPU: The Master of Versatility and Control<\/b><\/h3>\n
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The CPU is the primary “brain” or “manager” of any computing system.<\/span>9<\/span> It is composed of a small number of powerful, complex cores designed to excel at sequential, single-threaded tasks.<\/span>13<\/span> A significant portion of its silicon real estate is dedicated to large caches and sophisticated control logic, enabling it to execute a wide variety of instructions, run the operating system, and manage system resources with very low latency.<\/span>8<\/span> However, the very versatility that makes the CPU a master of general-purpose computing is its primary weakness for AI. Its architecture suffers from “limited parallelism,” making it profoundly inefficient at handling the thousands of simultaneous calculations required by neural networks.<\/span>9<\/span> In the context of the modern System-on-Chip (SoC), the CPU acts as the conductor, directing system operations and handling tasks that require complex, sequential logic, but it is not equipped for the heavy lifting of AI computation.<\/span><\/p>\n <\/p>\n
2.2 The GPU: The Powerhouse of Parallelism<\/b><\/h3>\n
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Originally designed to accelerate the rendering of graphics, the GPU’s architecture is fundamentally different from a CPU’s. It contains hundreds or even thousands of smaller, simpler cores optimized to perform the same operation on many different pieces of data simultaneously\u2014a model known as Single Instruction, Multiple Data (SIMD).<\/span>9<\/span> This massive parallelism made the GPU a natural fit for accelerating the training of deep learning models in data centers, reducing training times from weeks to hours.<\/span>11<\/span> However, for on-device inference, the GPU has two significant drawbacks. First, its high performance comes at the cost of high power consumption, which is detrimental to the battery life of mobile devices.<\/span>9<\/span> Second, while excellent at parallel math, its architecture is not fully optimized for the specific low-precision, data-flow-intensive nature of AI inference workloads.<\/span>16<\/span> The GPU is a parallel computing behemoth, but for on-device AI, it is often an inefficient, power-hungry tool.<\/span><\/p>\n <\/p>\n
2.3 The NPU: The Specialist in AI Efficiency<\/b><\/h3>\n
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The NPU is a purpose-built specialist, designed from the ground up to accelerate neural network computations with maximum efficiency.<\/span>6<\/span> It achieves a superior performance-per-watt metric by incorporating hardware and software optimizations specifically for AI workloads while shedding the general-purpose overhead inherent in CPUs and the graphics-centric features of GPUs.<\/span>1<\/span> Its architecture is tailored to excel at the repetitive, parallel matrix and convolution operations that constitute the vast majority of the work in running a neural network.<\/span>6<\/span> The NPU’s design philosophy is one of targeted specialization, trading the broad versatility of the CPU and the powerful but generic parallelism of the GPU for extreme efficiency within the narrow but increasingly critical domain of AI inference.<\/span><\/p>\n <\/p>\n
2.4 The System-on-Chip (SoC) Synergy: The Rise of Heterogeneous Computing<\/b><\/h3>\n
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In modern consumer devices, the CPU, GPU, and NPU are not discrete, competing components. Instead, they are integrated as co-processors onto a single semiconductor microchip known as a System-on-Chip (SoC).<\/span>6<\/span> This architecture enables a “heterogeneous computing” model, where the operating system and applications can intelligently offload specific tasks to the processor best suited for the job.<\/span>2<\/span><\/p>\nA typical scenario illustrates this synergy: during a video call, the CPU runs the operating system and the communication application, the GPU renders the user interface on the screen, and the NPU efficiently handles the AI-powered real-time background blur effect.<\/span>2<\/span> By assigning each task to the most efficient processor, this model maximizes overall system performance and, critically for mobile devices, conserves battery life. The NPU is therefore not a replacement for the CPU or GPU; it is the essential third pillar of the modern SoC that makes pervasive, responsive, and power-efficient on-device AI a reality.<\/span><\/p>\nThe maturation of this heterogeneous model elevates the strategic importance of the software layer that manages it. The key competitive differentiator is shifting from the raw performance of any single processor to the intelligence of the software scheduler and high-level APIs, such as Microsoft’s Windows ML or Apple’s CoreML.<\/span>5<\/span> The effectiveness of the entire system hinges on the ability of this software to seamlessly and efficiently orchestrate workloads across all three processing units. A poorly optimized scheduler could send an AI task to the inefficient CPU, completely negating the NPU’s power-saving benefits. Consequently, the companies that control these high-level programming frameworks and OS-level schedulers hold significant power to define the developer experience and ultimately determine how effectively the potential of the underlying silicon is translated into real-world performance.<\/span><\/p>\n <\/p>\n
Table 2.1: Comparative Analysis of Processor Architectures for AI Workloads<\/b><\/h3>\n
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\n\n\n| Feature<\/b><\/td>\n | Central Processing Unit (CPU)<\/b><\/td>\n | Graphics Processing Unit (GPU)<\/b><\/td>\n | Neural Processing Unit (NPU)<\/b><\/td>\n<\/tr>\n\n| Primary Architecture<\/b><\/td>\n | Sequential, latency-optimized<\/span><\/td>\n | Massively parallel, throughput-optimized<\/span><\/td>\n | Massively parallel, dataflow-optimized<\/span><\/td>\n<\/tr>\n\n| Core Design<\/b><\/td>\n | Few (2-64) powerful, complex cores<\/span><\/td>\n | Hundreds to thousands of simpler cores<\/span><\/td>\n | Thousands of specialized, simple MAC units<\/span><\/td>\n<\/tr>\n\n| Optimal Workload<\/b><\/td>\n | General-purpose tasks, OS, logic control<\/span><\/td>\n | Graphics rendering, large-scale parallel compute<\/span><\/td>\n | Neural network inference, matrix operations<\/span><\/td>\n<\/tr>\n\n| Key Strength for AI<\/b><\/td>\n | Versatility for model prototyping<\/span><\/td>\n | High-throughput for model training<\/span><\/td>\n | Unmatched power efficiency for inference<\/span><\/td>\n<\/tr>\n\n| Key Weakness for AI<\/b><\/td>\n | Limited parallelism, high cost to scale<\/span><\/td>\n | High power consumption, not fully optimized for inference<\/span><\/td>\n | Limited versatility, not suited for general tasks<\/span><\/td>\n<\/tr>\n\n| Dominant Data Precision<\/b><\/td>\n | High precision (e.g., FP32, FP64)<\/span><\/td>\n | Mixed precision (e.g., FP32, FP16)<\/span><\/td>\n | Low precision (e.g., INT8, FP16, INT4)<\/span><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n Sources: <\/span>6<\/span><\/p>\n <\/p>\n Section 3: Inside the Accelerator: A Technical Deep Dive into NPU Architecture<\/b><\/h2>\n <\/p>\n To understand how the NPU achieves its remarkable efficiency, it is necessary to examine its core architectural components. Unlike general-purpose processors, every aspect of an NPU’s design\u2014from its computational units to its memory subsystem\u2014is tailored for the specific demands of executing neural network models. This specialization is the key to its superior performance-per-watt.<\/span><\/p>\n <\/p>\n 3.1 The Engine of AI: Multiply-Accumulate (MAC) Arrays<\/b><\/h3>\n <\/p>\n The computational heart of an NPU is a vast array of simple, dedicated processing elements known as Multiply-Accumulate (MAC) units.<\/span>8<\/span> These units are designed to perform the most fundamental operation in a neural network: multiplying two numbers and adding the result to an accumulator. An NPU may integrate hundreds or even thousands of these MAC units.<\/span>8<\/span> They are often arranged in a grid-like structure, sometimes referred to as a systolic array, which is architecturally optimized to process the matrix multiplication and convolution operations that dominate deep learning algorithms.<\/span>1<\/span> Alongside these core MAC arrays, an NPU typically includes smaller, specialized hardware modules to accelerate other common neural network operations, such as activation functions (e.g., ReLU, Sigmoid) and pooling.<\/span>6<\/span> By dedicating vast amounts of silicon to these specific, massively repeated operations, the NPU achieves a density of AI-relevant computation that is orders of magnitude greater than what is possible with general-purpose CPU cores.<\/span><\/p>\n <\/p>\n 3.2 The Efficiency of Imprecision: The Role of Low-Precision Arithmetic<\/b><\/h3>\n <\/p>\n A defining characteristic of NPU architecture is its reliance on low-precision arithmetic. While scientific and general-purpose computing on CPUs often requires high-precision 32-bit or 64-bit floating-point numbers ($FP32$, $FP64$), research and practical application have shown that AI inference can achieve high accuracy using much less precise data types.<\/span>1<\/span> Consequently, NPUs are designed to operate natively on low-precision formats such as 8-bit integers ($INT8$), 16-bit floating-point numbers ($FP16$), and in some cases, even 4-bit integers ($INT4$).<\/span>5<\/span><\/p>\nThis is a critical design trade-off. Lowering the numerical precision dramatically reduces the complexity and energy consumption of the MAC units. It also shrinks the memory footprint of the AI model and lessens the demand on memory bandwidth, as more data can be transferred in a single cycle.<\/span>1<\/span> For on-device AI, where power and memory are constrained, this gain in efficiency comes at the cost of a negligible, and often imperceptible, impact on the final accuracy of the model’s predictions.<\/span><\/p>\n <\/p>\n 3.3 Taming the Bottleneck: Dataflow Architectures and Memory Hierarchies<\/b><\/h3>\n <\/p>\n In any high-performance computing system, the movement of data between memory and the processing units is a primary source of latency and power consumption.<\/span>26<\/span> An NPU’s MAC array can perform trillions of operations per second, but this capability is useless if the array is sitting idle, waiting for data. Therefore, a significant portion of NPU design focuses on creating an efficient memory and data-delivery system.<\/span><\/p>\nTo combat this bottleneck, NPUs feature large amounts of high-bandwidth on-chip static RAM (SRAM) or specialized caches that are physically located very close to the compute arrays.<\/span>1<\/span> This minimizes the distance data has to travel. Furthermore, NPUs employ novel “dataflow” architectures, which are sophisticated hardware-based scheduling systems designed to orchestrate the movement of model weights and input data (activations) through the memory hierarchy and into the compute engines. The goal is to ensure the MAC units are constantly supplied with work, maximizing their utilization and overall efficiency.<\/span>5<\/span> Some advanced designs further enhance this by using techniques like decoupled execute\/access, where Direct Memory Access (DMA) instructions to fetch data run concurrently with the calculation (CAL) instructions that process it, hiding memory latency.<\/span>28<\/span><\/p>\nThe entire architectural philosophy of a modern NPU can be understood as a direct assault on the fundamental physical constraint of energy consumption from data movement. Every key feature is a tactic aimed at solving this one problem. Low-precision math reduces the <\/span>amount<\/span><\/i> of data to be moved. On-chip SRAM reduces the <\/span>distance<\/span><\/i> data travels. Dataflow architectures reduce the <\/span>time<\/span><\/i> spent waiting for data. This reveals that an NPU is not merely a “matrix math accelerator” but a holistic system engineered around the principle of minimizing data transfer. Future innovations will likely focus even more on this area, with trends like in-memory computing and 3D stacking of memory and logic representing the next frontiers.<\/span>8<\/span><\/p>\n <\/p>\n 3.4 Advanced Architectural Optimizations<\/b><\/h3>\n <\/p>\n As NPU design matures, architects are incorporating more sophisticated techniques to further boost efficiency.<\/span><\/p>\n\n- Sparsity Acceleration:<\/b> Many AI models, after an optimization process called pruning, contain a large number of weight parameters that are zero. Sparsity acceleration is a hardware feature that allows the NPU to detect these zero-values and skip the corresponding multiplication operations entirely, saving both computation cycles and the energy that would have been wasted on a pointless calculation.<\/span>18<\/span><\/li>\n
- Dynamic Power Management:<\/b> Advanced NPUs feature dynamic voltage and frequency scaling (DVFS), which allows the hardware to intelligently adapt its power consumption and performance level to the demands of the current workload. During periods of low AI activity, the NPU can scale down to a very low-power state, and then instantly scale back up when an intensive task arrives.<\/span>18<\/span><\/li>\n
- On-the-Fly Decompression:<\/b> To reduce the memory required to store large models, weights are often compressed. Some NPU architectures can process these compressed weights directly, decompressing them on-the-fly within the hardware. This eliminates the need to first decompress the entire model into a large memory buffer, a significant advantage for memory-constrained edge devices.<\/span>24<\/span><\/li>\n<\/ul>\n
These features demonstrate a clear evolution in NPU design, moving beyond a singular focus on raw peak performance (measured in TOPS, or Trillions of Operations Per Second) to a more nuanced approach of intelligent, workload-aware power and efficiency management.<\/span><\/p>\n <\/p>\n Section 4: The NPU-Powered Experience: Applications and Use Cases in Consumer Devices<\/b><\/h2>\n <\/p>\n The integration of NPUs into consumer electronics has transitioned on-device AI from a theoretical concept to a tangible reality, enabling a host of new features and enhancing existing ones. This section surveys the key applications powered by NPUs across major device categories, highlighting the transformative impact on the user experience.<\/span><\/p>\n <\/p>\n 4.1 The Smartphone Revolution: Computational Photography and Intelligent Interaction<\/b><\/h3>\n <\/p>\n Smartphones are arguably the most mature market for NPUs, where these accelerators have become the engine for a wide array of AI-driven features.<\/span><\/p>\n\n- Computational Photography:<\/b> The NPU has transformed the smartphone camera from a simple optical sensor into a sophisticated computational imaging system. It powers features like Portrait Mode, which uses semantic segmentation to separate a subject from the background and apply an artificial blur; advanced scene recognition to automatically optimize camera settings; Night Mode, which intelligently fuses multiple exposures to create bright, clean images in low light; and security functions like Face ID, which relies on neural networks for biometric authentication.<\/span>1<\/span><\/li>\n
- Intelligent Interaction:<\/b> NPUs enable faster, more private, and more capable on-device voice assistants and natural language processing. This allows for real-time language translation, intelligent text suggestions, and voice commands that can be processed without an internet connection.<\/span>1<\/span><\/li>\n<\/ul>\n
Prominent examples of this technology include Apple’s Neural Engine in its A-series and M-series chips, Qualcomm’s Hexagon NPU within its Snapdragon platforms, and Google’s custom Tensor processors in its Pixel phones.<\/span>5<\/span><\/p>\n <\/p>\n 4.2 The Dawn of the AI PC: Redefining the Laptop Experience<\/b><\/h3>\n <\/p>\n The NPU is now a defining component of the “AI PC,” a new category of laptops designed with on-device AI at their core.<\/span>2<\/span> In this context, the NPU’s primary role is to accelerate AI features that enhance productivity and collaboration while preserving battery life and system responsiveness.<\/span><\/p>\n\n- Enhanced Communication:<\/b> A primary use case is the acceleration of Windows Studio Effects in video conferencing applications. Features such as real-time background blur, automatic framing, eye contact correction, and advanced voice noise suppression are offloaded to the NPU. This ensures a smooth, high-quality video call experience without bogging down the CPU or GPU, which remain free to handle other tasks.<\/span>2<\/span><\/li>\n
- OS-Level Intelligence:<\/b> With sufficient performance (e.g., the 40+ TOPS requirement for Microsoft’s Copilot+ PCs <\/span>20<\/span>), NPUs enable new capabilities integrated directly into the operating system. These include on-device Live Captions with real-time translation, semantic search that understands natural language queries, and generative AI tools like Cocreator in Paint.<\/span>34<\/span> Microsoft’s Recall feature, which creates a searchable timeline of user activity, is an example of a pervasive background task made feasible by the NPU’s efficiency.<\/span>34<\/span><\/li>\n<\/ul>\n
The evolution of NPU-powered applications is occurring in two distinct phases. The first phase involved the <\/span>enhancement<\/span><\/i> of existing features, such as making background blur more power-efficient.<\/span>35<\/span> The current, second phase is one of <\/span>enablement<\/span><\/i>, where more powerful NPUs are making entirely new, previously impractical on-device experiences like Recall and offline generative AI possible.<\/span>36<\/span> This creates a powerful feedback loop: new hardware capabilities inspire new software, which in turn drives consumer demand for the next generation of hardware, rapidly accelerating the pace of innovation.<\/span><\/p>\n <\/p>\n 4.3 The Intelligent Ecosystem: IoT, Wearables, and Smart Homes<\/b><\/h3>\n <\/p>\n The NPU’s hallmark of low power consumption makes it an ideal processor for the vast and growing ecosystem of connected devices at the edge.<\/span><\/p>\n\n- Smart Home Devices:<\/b> In smart speakers, NPUs can handle local processing of voice commands, reducing latency and allowing for basic functionality even when the internet is down.<\/span>6<\/span> In smart security cameras, an NPU can perform on-device person, package, and vehicle detection, sending alerts to the user without having to stream sensitive video footage to a cloud server for analysis.<\/span>1<\/span><\/li>\n
- Wearables and Health Tech:<\/b> Wearable devices like smartwatches and fitness trackers can leverage NPUs for advanced health monitoring, such as analyzing sensor data to detect anomalies in heart rhythms or sleep patterns.<\/span>1<\/span><\/li>\n
- Broader IoT:<\/b> Across the IoT landscape, from industrial sensors to autonomous drones, NPUs provide the on-device intelligence needed for real-time analytics and decision-making in environments with strict power and bandwidth limitations.<\/span>11<\/span><\/li>\n<\/ul>\n
In these applications, the NPU is a critical enabler of both real-time responsiveness and user privacy, allowing devices to be intelligent and useful without a constant, umbilical connection to the cloud.<\/span><\/p>\n <\/p>\n 4.4 The Privacy and Security Advantage of On-Device AI<\/b><\/h3>\n <\/p>\n A recurring and paramount benefit of NPU-driven, on-device AI is the fundamental enhancement of user privacy and data security. In a cloud-based AI model, user data must be sent to a remote server for processing. This transmission creates potential vulnerabilities for data breaches, interception, or unauthorized use.<\/span>22<\/span><\/p>\nThe NPU obviates this need. By processing data locally, sensitive information\u2014such as a user’s face for biometric unlock, the video feed from a home camera, private documents being summarized, or voice commands spoken to an assistant\u2014never has to leave the physical confines of the device.<\/span> | | | | | | |
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