{"id":7891,"date":"2025-11-28T15:02:36","date_gmt":"2025-11-28T15:02:36","guid":{"rendered":"https:\/\/uplatz.com\/blog\/?p=7891"},"modified":"2025-11-28T22:53:13","modified_gmt":"2025-11-28T22:53:13","slug":"the-post-silicon-roadmap-atomic-level-switching-quantum-effect-devices-and-the-manufacturing-of-next-generation-processors","status":"publish","type":"post","link":"https:\/\/uplatz.com\/blog\/the-post-silicon-roadmap-atomic-level-switching-quantum-effect-devices-and-the-manufacturing-of-next-generation-processors\/","title":{"rendered":"The Post-Silicon Roadmap: Atomic-Level Switching, Quantum-Effect Devices, and the Manufacturing of Next-Generation Processors"},"content":{"rendered":"

Part 1: The End of the Silicon Era and the Rise of Quantum-Scale Devices<\/b><\/h2>\n

Executive Summary: The Two “Quantum” Revolutions<\/b><\/h3>\n

Next-generation processors are redefining computing through atomic-level switching, quantum-effect devices, and post-silicon manufacturing innovations.<\/p>\n

The semiconductor industry is at a foundational inflection point. For half a century, its trajectory has been defined by the predictable scaling of the silicon-based metal-oxide-semiconductor field-effect transistor (MOSFET).<\/span>1<\/span> This scaling, however, is colliding with fundamental physical and economic limits. In response, the industry is diverging onto two distinct “beyond-silicon” trajectories, both of which are frequently and confusingly labeled “quantum.” This report will disambiguate these two paths, analyze their underlying technologies, and provide a strategic forecast for the future of computation.<\/span><\/p>\n

It is a common misconception that quantum mechanics is new to electronics; in fact, all modern computing is “quantum” in nature. The very existence of energy bands, semiconductivity, and the operation of the first diodes and transistors are phenomena only explainable by quantum mechanics.<\/span>2<\/span> The current shift, however, is one of intent. Instead of building devices that operate <\/span>despite<\/span><\/i> certain quantum effects (like leakage), engineers are now designing devices that <\/span>explicitly leverage<\/span><\/i> specific quantum phenomena to function.<\/span><\/p>\n

\"\"<\/p>\n

https:\/\/uplatz.com\/course-details\/bundle-combo-data-science-with-python-and-r\/414<\/a><\/p>\n

These two divergent paths are:<\/span><\/p>\n

    \n
  1. Path 1: The Quantum-Effect Classical Switch.<\/b> This is the pursuit of a “better switch” to continue the roadmap for classical computing (e.g., high-performance computing (HPC), mobile, and Internet of Things (IoT)). This path leverages quantum-mechanical principles like <\/span>quantum tunneling<\/b> and <\/span>Coulomb blockade<\/b> to create a more efficient <\/span>binary<\/span><\/i> (0\/1) transistor. The goal is to overcome the fundamental power and scaling limitations of the silicon MOSFET. This domain includes Tunnel Field-Effect Transistors (TFETs), Single-Electron Transistors (SETs), Carbon Nanotube FETs (CNFETs), and 2D-material FETs.<\/span>3<\/span><\/li>\n
  2. Path 2: The True Quantum Processor.<\/b> This is the pursuit of a “new computer” based on a different computational paradigm. This path leverages the quantum-mechanical properties of <\/span>superposition<\/span><\/i> (where a “qubit” can be 0 and 1 simultaneously) and <\/span>entanglement<\/span><\/i> to perform calculations.<\/span>6<\/span> In this context, the “transistor” has been repurposed in two ways: either as the <\/span>qubit itself<\/b> (e.g., a silicon FinFET structure used to trap a single electron) or as an ultra-sensitive <\/span>readout sensor<\/b> (e.g., an SET) for the qubit.<\/span>8<\/span><\/li>\n<\/ol>\n

    This report will analyze the physics, materials, manufacturing, and architectural implications of both paths. It will demonstrate that the future of computation is not a replacement but a <\/span>hybridization<\/span><\/i>, where these two paths will ultimately converge in 3D-heterogeneously integrated systems.<\/span><\/p>\n

     <\/p>\n

    The Scaling Imperative: Beyond the Boltzmann Tyranny<\/b><\/h3>\n

     <\/p>\n

    The primary driver for this paradigm shift is the failure of classical silicon scaling. The silicon MOSFET, the workhorse of the digital age, has hit a fundamental physical wall.<\/span>1<\/span><\/p>\n

     <\/p>\n

    The Physics Wall: The “Boltzmann Tyranny”<\/b><\/h4>\n

     <\/p>\n

    The classical transistor is a <\/span>thermal<\/span><\/i> device. It operates by using a gate voltage to lower an energy barrier, allowing electrons to “boil” over it via <\/span>thermionic emission<\/b>\u2014a process driven by thermal energy.<\/span>3<\/span> This thermal mechanism imposes a fundamental limit on the transistor’s “steepness,” or how sharply it can switch from “off” to “on.”<\/span><\/p>\n

    This limit is known as the <\/span>subthreshold swing (SS)<\/b>, which measures the gate voltage ($V_G$) required to increase the drain current ($I_D$) by one decade (a factor of 10). At room temperature, the physics of thermionic emission dictates a minimum theoretical SS of 60 millivolts per decade (mV\/dec).<\/span>3<\/span> This is the “Boltzmann tyranny”.<\/span>11<\/span><\/p>\n

    For decades, this was not a problem. But as transistors shrink, their supply voltage ($V_{DD}$) must also be reduced to manage power density and heat.<\/span>4<\/span> With a “floor” of 60 mV\/dec on the switching steepness, it becomes impossible to scale $V_{DD}$ below a certain point (e.g., sub-0.5V) and still have the transistor turn “off” completely.<\/span>4<\/span> The result is a massive, exponential increase in <\/span>static leakage current<\/b>, which now accounts for a significant portion of a chip’s total power consumption.<\/span>12<\/span> This has led to the “dark silicon” problem, where large portions of a chip must be kept powered down to avoid meltdown.<\/span>13<\/span> To continue scaling, a new device is required\u2014one whose switching mechanism is <\/span>not<\/span><\/i> thermal and can, therefore, achieve a “super-steep” SS (sub-60 mV\/dec).<\/span>3<\/span><\/p>\n

     <\/p>\n

    The Economic Wall: Rock’s Law<\/b><\/h4>\n

     <\/p>\n

    Parallel to this physics crisis is an economic one. <\/span>Moore’s Law<\/b>\u2014the observation that transistor density doubles at a predictable cadence\u2014is enabled by its “darker side,” <\/span>Rock’s Law<\/b>.<\/span>14<\/span> Rock’s Law states that the <\/span>cost<\/span><\/i> of the semiconductor fabrication plant (fab) required to produce these chips rises exponentially with each generation.<\/span>14<\/span><\/p>\n

    This is the price of pushing matter to atomic precision. A state-of-the-art fab now costs between $10 billion and $20 billion.<\/span>14<\/span> A single High-NA Extreme Ultraviolet (EUV) lithography scanner, the most advanced patterning tool, costs over $400 million.<\/span>14<\/span><\/p>\n

    The industry is therefore trapped in a <\/span>“CMOS Pincer”<\/b>:<\/span><\/p>\n

      \n
    1. The <\/span>physics<\/span><\/i> of the MOSFET (Boltzmann Tyranny) demands a revolutionary <\/span>new device<\/b>.<\/span>3<\/span><\/li>\n
    2. The <\/span>economics<\/span><\/i> of the fab (Rock’s Law) demands that this new device be <\/span>CMOS-compatible<\/b>, meaning it must be manufacturable using the existing, multi-trillion-dollar infrastructure.<\/span>14<\/span><\/li>\n<\/ol>\n

      This economic “activation energy” is the primary filter for all “beyond silicon” candidates. The industry’s formal acknowledgments of this crisis, such as the U.S. Department of Energy’s “Energy Efficiency Scaling for Two Decades” (EES2) roadmap and the International Roadmap for Devices and Systems (IRDS), are actively scouting for CMOS-compatible replacements, with TFETs, CNFETs, and 2D materials as prime candidates.<\/span>15<\/span><\/p>\n

       <\/p>\n

      Part 2: The Next Classical Transistor: Devices Based on Quantum-Mechanical Principles<\/b><\/h2>\n

       <\/p>\n

      This section analyzes the leading candidates for Path 1: a “better switch” that leverages quantum mechanics to overcome the 60 mV\/dec limit and replace the classical MOSFET.<\/span><\/p>\n

       <\/p>\n

      Tunnel Field-Effect Transistors (TFETs): Breaking the Thermal Limit<\/b><\/h3>\n

       <\/p>\n

      The Tunnel Field-Effect Transistor (TFET) is the most direct challenger to the MOSFET’s physical limitations.<\/span><\/p>\n

       <\/p>\n

      Principle of Operation<\/b><\/h4>\n

       <\/p>\n

      Unlike a MOSFET, which relies on thermionic emission <\/span>over<\/span><\/i> a barrier, the TFET is a pure <\/span>quantum-mechanical<\/span><\/i> switch.<\/span>3<\/span> It operates by using the gate voltage to modulate the <\/span>Band-to-Band Tunneling (BTBT)<\/b> of electrons <\/span>through<\/span><\/i> an energy barrier.<\/span>4<\/span><\/p>\n

      In the “off” state, the conduction and valence bands are misaligned, and no tunneling is possible. As gate voltage is applied, the bands are shifted, and a “tunneling window” opens, allowing electrons to quantum-tunnel from the source’s valence band to the channel’s conduction band.<\/span>3<\/span> Because this switching mechanism is non-thermal, its subthreshold swing is <\/span>not<\/span><\/i> limited by the 60 mV\/dec “Boltzmann” limit.<\/span>12<\/span> This allows for a “super-steep” SS and, in theory, a dramatic reduction in standby power consumption by enabling ultra-low supply voltages.<\/span>4<\/span><\/p>\n

       <\/p>\n

      The Primary Challenge: The “TFET Trade-off”<\/b><\/h4>\n

       <\/p>\n

      For years, TFETs have been stalled by a fundamental trade-off: while they are excellent at being “off” (low leakage), the quantum tunneling effect is a low-probability event. This results in an inherently <\/span>low ON-current ($I_{on}$)<\/b>.<\/span>20<\/span> This low drive current makes them too slow for high-speed computation, relegating them to niche low-power applications. The central goal of TFET research is to solve this low $I_{on}$ problem while retaining the steep SS.<\/span><\/p>\n

       <\/p>\n

      Breakthrough 1: The Negative Capacitance (NC-FET) “Hack”<\/b><\/h4>\n

       <\/p>\n

      A major breakthrough has been the development of the <\/span>Negative Capacitance TFET (NC-TFET)<\/b>.<\/span>22<\/span> This is a hybrid device that integrates a thin layer of <\/span>ferroelectric<\/span><\/i> material (such as PZT or silicon-doped HfO$_2$) into the gate stack.<\/span>22<\/span><\/p>\n

      This ferroelectric material exhibits a “negative capacitance” (NC), an unstable state that can be stabilized when paired with the positive capacitance of the transistor gate.<\/span>22<\/span> The profound result is an <\/span>internal voltage amplification<\/b> effect.<\/span>22<\/span> A small change in the <\/span>external<\/span><\/i> gate voltage (e.g., 10 mV) is “stepped-up” by the ferroelectric layer, applying a much larger effective voltage (e.g., >60 mV) directly to the TFET’s tunneling junction.<\/span>22<\/span><\/p>\n

      This is a “physics hack” that accomplishes two things simultaneously:<\/span><\/p>\n

        \n
      1. It provides a <\/span>super-steep<\/span><\/i> external SS, with experimental values demonstrated <\/span>down to 10 mV\/decade<\/span><\/i>.<\/span>22<\/span><\/li>\n
      2. It dramatically <\/span>boosts the tunneling probability<\/span><\/i> by applying a much larger internal electric field, solving the low $I_{on}$ problem.<\/span>22<\/span><\/li>\n<\/ol>\n

        This NC-TFET concept, which combines the NC effect with the BTBT mechanism, represents one of the most promising paths to a high-performance, super-steep transistor.<\/span>22<\/span><\/p>\n

         <\/p>\n

        Breakthrough 2: The 2D Materials Solution<\/b><\/h4>\n

         <\/p>\n

        A parallel solution to the TFET’s $I_{on}$ problem lies in materials science. TFET performance is highly dependent on creating an <\/span>abrupt<\/span><\/i> junction and an <\/span>intense<\/span><\/i> electric field at the tunneling point.<\/span>20<\/span> Atomically-thin two-dimensional (2D) materials, particularly <\/span>Transition Metal Dichalcogenides (TMDs)<\/b> like MoS$_2$ and WSe$_2$, are the ideal channel material for this.<\/span>23<\/span><\/p>\n

        This material-device synergy is critical. The atomic-scale thickness of 2D TMDs (as thin as three atoms) provides the “ultimate” electrostatic integrity, allowing the gate to exert perfect, “tight” control over the channel and induce the sharp band-bending needed for efficient tunneling.<\/span>21<\/span><\/p>\n

        Furthermore, TFETs perform best as <\/span>heterojunctions<\/b> (junctions of two different semiconductor materials) to engineer the band alignments for tunneling.<\/span>26<\/span> Stacking different 2D materials (e.g., a WSe$_2$\/MoS$_2$ junction) creates a “van der Waals heterojunction”.<\/span>28<\/span> Unlike 3D junctions (e.g., SiGe-on-Si), these 2D-stacked junctions are <\/span>atomically clean<\/span><\/i> and free of the lattice-mismatch defects that kill device performance.<\/span>26<\/span><\/p>\n

        This combination\u2014perfect electrostatics (from 2D thinness) and perfect junctions (from 2D stacking)\u2014is the key to fabricating high-performance TFETs that solve the low $I_{on}$ problem.<\/span>26<\/span> Research into MoS$_2$-based TFETs has demonstrated their potential for sub-60mV\/dec performance, and a trade-off analysis between monolayer and multilayer MoS$_2$ shows that while monolayers give the best SS, multilayers (e.g., 6-layer) can provide a higher ON-current.<\/span>29<\/span> These 2D TFETs have already been used to demonstrate basic VLSI circuits like inverters and half-adders.<\/span>33<\/span><\/p>\n

         <\/p>\n

        Single-Electron Transistors (SETs): The Ultimate Scaling Limit<\/b><\/h3>\n

         <\/p>\n

        The Single-Electron Transistor (SET) represents the theoretical ultimate limit of transistor scaling, a device that operates by controlling the flow of <\/span>one electron at a time<\/span><\/i>.<\/span>34<\/span><\/p>\n

         <\/p>\n

        Principle of Operation: The Coulomb Blockade<\/b><\/h4>\n

         <\/p>\n

        An SET is a three-terminal device where a small conductive “island,” or <\/span>quantum dot<\/b>, is separated from the source and drain electrodes by two thin tunnel junctions.<\/span>34<\/span> Its operation is governed by a quantum-mechanical phenomenon called the <\/span>Coulomb blockade<\/b>.<\/span>34<\/span><\/p>\n

        The act of adding a single electron to the tiny island requires a specific amount of charging energy ($E_C = \\frac{e^2}{2C}$), where $C$ is the island’s tiny self-capacitance.<\/span>34<\/span> If the incoming electron’s energy (from thermal energy $k_B T$ or bias voltage $V_{bias}$) is <\/span>less<\/span><\/i> than this charging energy, the electron is “blocked,” and no current can flow. This is the “off” state.<\/span>34<\/span><\/p>\n

        The gate electrode is capacitively coupled to the island and is used to precisely tune the island’s electrochemical potential.<\/span>34<\/span> By applying a specific gate voltage, the blockade can be lifted, allowing <\/span>exactly one<\/span><\/i> electron to tunnel onto the island, and then tunnel off to the drain. The blockade is then re-established until the next cycle. Current flows in this discrete, one-by-one fashion.<\/span>34<\/span><\/p>\n

         <\/p>\n

        Analysis: The “Wrong Tool” for Logic, The “Right Tool” for Sensing<\/b><\/h4>\n

         <\/p>\n

        While the SET is a marvel of physics, it is a <\/span>poor<\/span><\/i> candidate for general-purpose logic. The conditions for observing the Coulomb blockade are severe:<\/span><\/p>\n

          \n
        1. Cryogenic Operation:<\/b> The thermal energy must be much lower than the charging energy ($k_B T \\ll \\frac{e^2}{2C}$), which for practical devices means operation at liquid helium or millikelvin temperatures.<\/span>34<\/span><\/li>\n
        2. Low Speed:<\/b> To ensure the electron is properly “confined” to the island, the tunnel barriers must have high resistance ($R_t \\gg \\frac{h}{e^2} \\approx 25.8 k\\Omega$), which inherently limits the current and thus the switching speed.<\/span>34<\/span><\/li>\n
        3. Noise Sensitivity:<\/b> The device’s state is controlled by a single electron. This makes it exquisitely sensitive to any stray background charges or “charge noise,” a critical problem in a dense chip environment.<\/span><\/li>\n<\/ol>\n

          This analysis reveals a critical pivot. The SET’s “weakness” as a logic device\u2014its extreme sensitivity to its electrostatic environment\u2014is its <\/span>greatest strength<\/span><\/i> as a sensor. This makes the SET the leading technology for the high-fidelity, non-destructive <\/span>readout<\/span><\/i> of a quantum qubit’s state, a concept central to Part 4 of this report.<\/span>10<\/span><\/p>\n

           <\/p>\n

          Atomic and Molecular-Scale Switches: The Research Frontier<\/b><\/h3>\n

           <\/p>\n

          The absolute frontier of “Path 1” involves fabricating switches from single atoms or molecules. These devices are not just smaller transistors; they are fundamentally <\/span>different<\/span><\/i> computational elements.<\/span><\/p>\n

           <\/p>\n

          The Single-Atom Transistor<\/b><\/h4>\n

           <\/p>\n

          In a landmark experiment, researchers fabricated a transistor where the active component was a <\/span>single phosphorus (P) dopant atom<\/b> deterministically placed within a silicon crystal.<\/span>36<\/span><\/p>\n

          The fabrication process itself is a technological marvel, relying on <\/span>Scanning Tunneling Microscope (STM) lithography<\/b>.<\/span>37<\/span><\/p>\n

            \n
          1. A silicon (Si(100)) surface is passivated with a “resist” layer of hydrogen atoms.<\/span>37<\/span><\/li>\n
          2. The tip of an STM is used to “write” a pattern by selectively desorbing individual hydrogen atoms, exposing the reactive silicon dangling bonds underneath with atomic precision.<\/span>37<\/span><\/li>\n
          3. The chamber is exposed to phosphine ($\\text{PH}_3$) gas. The $\\text{PH}_3$ molecules stick <\/span>only<\/span><\/i> to the desorbed patches.<\/span>37<\/span><\/li>\n
          4. A brief thermal anneal incorporates the phosphorus atom into the silicon lattice at that precise location.<\/span>37<\/span><\/li>\n<\/ol>\n

            This technique was used to place a single P atom between two heavily-doped silicon leads, creating a functional single-atom transistor.<\/span>37<\/span> This was also demonstrated for creating SETs with atomically precise tunnel gaps.<\/span>39<\/span><\/p>\n

             <\/p>\n

            The Single-Molecule Transistor (Quantum Interference)<\/b><\/h4>\n

             <\/p>\n

            A more recent breakthrough, published in <\/span>Nature Nanotechnology<\/span><\/i> in March 2024, demonstrated a transistor where the conductive channel is a <\/span>single molecule<\/b> (a zinc porphyrin molecule) sandwiched between two graphene electrodes.<\/span>42<\/span><\/p>\n

            The switching mechanism in this device is not a thermal barrier (MOSFET) or a tunneling barrier (TFET). Instead, it relies on <\/span>quantum interference<\/b>.<\/span>42<\/span> The gate voltage is used to control the phase of the electron’s wavefunction as it passes through the molecule. By tuning the gate, the electron’s pathways can be made to interfere <\/span>constructively<\/span><\/i> (the “on” state, with high current) or <\/span>destructively<\/span><\/i> (the “off” state, where the electron’s wavefunction cancels itself out, leading to very low current).<\/span>42<\/span><\/p>\n

             <\/p>\n

            Implications: Beyond Binary Computation<\/b><\/h4>\n

             <\/p>\n

            These atomic-scale devices reveal a new computational paradigm. The single-atom transistor’s transport measurements (at cryogenic temperatures) show <\/span>discrete quantum energy levels<\/span><\/i>, not a simple binary on\/off state.<\/span>36<\/span> The single-molecule transistor operates on wave interference, an analog phenomenon.<\/span><\/p>\n

            This behavior\u2014multi-state, analog, or wave-based\u2014is a poor fit for traditional binary logic. However, it is <\/span>exactly<\/span><\/i> what is required for <\/span>non-von Neumann<\/b> computing architectures, which will be discussed in Part 5. These devices are ideal candidates for building hardware-based <\/span>neuromorphic computers<\/b> (which seek to emulate the analog, multi-level “synaptic” behavior of a biological neuron) and <\/span>in-memory computing<\/b> systems.<\/span>43<\/span><\/p>\n

            Table 1: Comparative Analysis of “Beyond Silicon” Transistor Candidates (For Classical Logic)<\/b><\/p>\n

             <\/p>\n\n\n\n\n\n\n\n\n\n
            Device<\/b><\/td>\nOperating Principle<\/b><\/td>\nKey Metric<\/b><\/td>\nPrimary Advantage<\/b><\/td>\nPrimary Challenge<\/b><\/td>\nKey Materials<\/b><\/td>\nTRL<\/b><\/td>\n<\/tr>\n
            FinFET (Baseline)<\/b><\/td>\nThermionic Emission <\/span>1<\/span><\/td>\nSS $\\approx$ 60-70 mV\/dec<\/span><\/td>\nMature, Scalable (EUV)<\/span><\/td>\nPower\/Leakage (Boltzmann Tyranny) <\/span>3<\/span><\/td>\nSilicon, SiGe<\/span><\/td>\n9<\/span><\/td>\n<\/tr>\n
            TFET<\/b><\/td>\nBand-to-Band Tunneling (BTBT) <\/span>3<\/span><\/td>\nSS < 60 mV\/dec <\/span>19<\/span><\/td>\nUltra-low standby power<\/span><\/td>\nLow ON-current ($I_{on}$) <\/span>20<\/span><\/td>\nSi, Ge, III-V<\/span><\/td>\n5-6<\/span><\/td>\n<\/tr>\n
            NC-TFET<\/b><\/td>\nBTBT + Negative Capacitance <\/span>22<\/span><\/td>\nSS < 10 mV\/dec <\/span>22<\/span><\/td>\n“Super-steep” slope, high $I_{on}$<\/span><\/td>\nComplex material stack, reliability<\/span><\/td>\nIII-V\/2D-TMD + HfO$_2$, PZT <\/span>22<\/span><\/td>\n4-5<\/span><\/td>\n<\/tr>\n
            SET<\/b><\/td>\nCoulomb Blockade <\/span>34<\/span><\/td>\nSingle-electron switching<\/span><\/td>\nUltimate scaling, high sensitivity<\/span><\/td>\nCryogenic, low current, noise sensitive <\/span>34<\/span><\/td>\nSilicon, GaAs<\/span><\/td>\n3 (for logic); 6 (for sensors)<\/span><\/td>\n<\/tr>\n
            CNFET<\/b><\/td>\nBallistic Transport <\/span>45<\/span><\/td>\n7-10x Energy-Delay Product <\/span>46<\/span><\/td>\nHighest speed & energy efficiency<\/span><\/td>\nMaterial purity, placement density <\/span>5<\/span><\/td>\nCarbon Nanotubes (CNTs)<\/span><\/td>\n6-7 (VLSI demo)<\/span><\/td>\n<\/tr>\n
            2D-TMD FET<\/b><\/td>\nThermionic Emission<\/span><\/td>\nSS $\\approx$ 60 mV\/dec<\/span><\/td>\nUltimate thickness (no SCEs) <\/span>24<\/span><\/td>\nWafer-scale growth, contact resistance<\/span><\/td>\nMoS$_2$, WSe$_2$ <\/span>23<\/span><\/td>\n5-6<\/span><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

            Part 3: The “New Silicon”: Materials and Fabrication at the Atomic Scale<\/b><\/h2>\n

             <\/p>\n

            The success of any new transistor (Path 1) or qubit (Path 2) is entirely dependent on the ability to manufacture it at scale. This requires a new generation of materials and fabrication techniques that bridge the gap from lab-scale prototypes to 300mm wafer production.<\/span><\/p>\n

             <\/p>\n

            Carbon Nanotube Field-Effect Transistors (CNFETs): The “Drop-In” Successor<\/b><\/h3>\n

             <\/p>\n

            The Carbon Nanotube Field-Effect Transistor (CNFET) has emerged as the leading “drop-in” replacement for silicon in high-performance logic.<\/span><\/p>\n

             <\/p>\n

            The Promise<\/b><\/h4>\n

             <\/p>\n

            A carbon nanotube is a sheet of graphene (a 1-atom-thick hexagonal lattice of carbon) rolled into a cylinder.<\/span>49<\/span> As a transistor channel, this quasi-one-dimensional structure is near-perfect:<\/span><\/p>\n