bundle-combo-sap-s4hana-sales-and-s4hana-logistics By uplatz<\/a><\/h3>\n2. The Physics of Attention and the GPU Memory Hierarchy<\/b><\/h2>\n
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To fully appreciate the necessity and ingenuity of IO-aware variants, one must first quantify the inefficiency inherent in standard attention implementations and map these operations onto the physical reality of modern accelerators.<\/span><\/p>\n <\/p>\n
2.1 The Standard Attention Bottleneck<\/b><\/h3>\n
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The standard self-attention mechanism computes the output $O$ as:<\/span><\/p>\n <\/p>\n
$$O = \\text{softmax}\\left(\\frac{QK^T}{\\sqrt{d}}\\right)V$$<\/span><\/p>\n <\/p>\n
where $Q$ (Query), $K$ (Key), and $V$ (Value) are input matrices of shape $(N, d)$, with $N$ representing the sequence length and $d$ the head dimension.<\/span><\/p>\nIn a standard PyTorch or TensorFlow implementation, this equation is executed operation-by-operation, leading to the full materialization of intermediate matrices in HBM.<\/span><\/p>\n\n- MatMul 1:<\/b> $S = QK^T$ produces a matrix of shape $(N, N)$. This matrix is written to HBM.<\/span><\/li>\n
- Masking\/Softmax:<\/b> The matrix $S$ is read from HBM, the softmax function is applied to produce the probability matrix $P$, and $P$ is written back to HBM.<\/span><\/li>\n
- MatMul 2:<\/b> $P$ and $V$ are read from HBM to compute $O = PV$, which is written to HBM.<\/span><\/li>\n<\/ol>\n
For a sequence length $N = 100,000$, the intermediate matrix $S$ (assuming FP16 precision) would require roughly 20GB of memory. Storing $P$ requires another 20GB. The sheer volume of data movement\u2014reading and writing 40GB of intermediates just to perform relatively simple arithmetic\u2014overwhelms the memory bandwidth. On an NVIDIA A100 GPU with approximately 1.5 TB\/s of bandwidth, simply reading these matrices takes significantly longer than the matrix multiplications themselves, pushing the arithmetic intensity into a regime where the GPU is almost entirely memory-bound.<\/span>1<\/span><\/p>\n <\/p>\n
2.2 The GPU Memory Hierarchy: HBM vs. SRAM<\/b><\/h3>\n
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The central thesis of IO-aware attention is that the GPU memory hierarchy is asymmetric.<\/span><\/p>\n\n- High Bandwidth Memory (HBM):<\/b> This is the main memory of the GPU (e.g., 40GB or 80GB on an A100). While “High Bandwidth” compared to system RAM, it is slow relative to the compute core’s appetite for data. Bandwidth is typically in the range of 1.5\u20133.35 TB\/s.<\/span><\/li>\n
- Static Random Access Memory (SRAM):<\/b> This is the on-chip memory, often referred to as L1\/shared memory. It is incredibly fast (19 TB\/s or higher) but extremely small (roughly 192KB per Streaming Multiprocessor, totaling perhaps 20-50MB across the entire GPU).<\/span>1<\/span><\/li>\n<\/ul>\n
Standard attention implementations fail to utilize SRAM effectively for large $N$ because the monolithic $N \\times N$ matrices cannot fit. Consequently, they default to using HBM as the scratchpad, incurring the heavy penalty of off-chip communication. IO-aware algorithms are designed specifically to exploit this hierarchy by keeping the large intermediate matrices “virtual”\u2014computing them block-by-block within SRAM and never allowing the full matrix to touch HBM.<\/span>3<\/span><\/p>\n3. FlashAttention-1: The Foundation of Tiling and Recomputation<\/b><\/h2>\n
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FlashAttention-1 (v1) represented a radical departure from standard deep learning compiler optimizations. Rather than relying on heuristic-based kernel fusion provided by frameworks like XLA or TorchScript, it introduced a mathematically exact algorithm designed explicitly for the GPU\u2019s memory asymmetry.<\/span><\/p>\n <\/p>\n
3.1 Tiling and Kernel Fusion<\/b><\/h3>\n
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The primary mechanism of FlashAttention-1 is <\/span>tiling<\/b>. The algorithm fundamentally restructures the matrix multiplication loops. Instead of computing the full $S$ matrix, it splits the Query ($Q$), Key ($K$), and Value ($V$) matrices into blocks ($Q_i, K_j, V_j$) that are small enough to fit entirely within the GPU’s SRAM.<\/span><\/p>\nThe computation proceeds as follows:<\/span><\/p>\n\n- Load a block of Queries $Q_i$ from HBM to SRAM.<\/span><\/li>\n
- Load a block of Keys $K_j$ and Values $V_j$ from HBM to SRAM.<\/span><\/li>\n
- Compute the attention scores $S_{ij} = Q_i K_j^T$ on-chip.<\/span><\/li>\n
- Apply the softmax operation on-chip to obtain $P_{ij}$.<\/span><\/li>\n
- Multiply by values $P_{ij} V_j$ and accumulate the result into an output block $O_i$ residing in SRAM.<\/span><\/li>\n
- Repeat for all $K, V$ blocks.<\/span><\/li>\n
- Finally, write the completed output block $O_i$ to HBM.<\/span><\/li>\n<\/ol>\n
Crucially, the intermediate blocks $S_{ij}$ and $P_{ij}$ are discarded immediately after use. They are never written to HBM. This <\/span>kernel fusion<\/b> collapses the multiple read\/write passes of standard attention into a single pass over the inputs and one write of the output. The memory complexity for the attention mechanism drops from $O(N^2)$ to $O(N)$\u2014linear in sequence length\u2014because the storage requirement is now independent of the $N \\times N$ interaction matrix.<\/span>1<\/span><\/p>\n <\/p>\n
3.2 Statistics for Online Softmax<\/b><\/h3>\n
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A challenge with tiling is that the Softmax function is inherently global; computing the probability for a single query token requires normalizing against the sum of exponentials of <\/span>all<\/span><\/i> keys ($ \\sum e^{s_{ik}} $). Since FlashAttention processes keys in blocks, it cannot see the full sum at once.<\/span><\/p>\nTo solve this, FlashAttention-1 employs the <\/span>Online Softmax<\/b> technique (a variant of the Safe Softmax algorithm). It maintains running statistics\u2014specifically the maximum score seen so far ($m$) and the running sum of exponentials ($\\ell$)\u2014for each query. As new blocks of keys are processed, these statistics are updated, and the accumulated output is rescaled to reflect the new global max. This ensures that the final output is mathematically identical to the standard Softmax attention, with no approximation error.<\/span>3<\/span><\/p>\n <\/p>\n
3.3 Recomputation in the Backward Pass<\/b><\/h3>\n
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Perhaps the most counter-intuitive innovation in FlashAttention-1 is the use of <\/span>recomputation<\/b> to accelerate the backward pass (training). In standard backpropagation, the attention probability matrix $P$ computed during the forward pass is cached in HBM to be used for calculating gradients. For long sequences, storing $P$ reintroduces the $N^2$ memory bottleneck.<\/span><\/p>\nFlashAttention-1 circumvents this by discarding $P$ after the forward pass. Instead, it saves only the lightweight normalization statistics ($m$ and $\\ell$) which scale linearly with $N$. During the backward pass, the algorithm re-loads $Q, K, V$ from HBM to SRAM and <\/span>re-computes<\/span><\/i> the attention scores and probabilities on-the-fly to calculate gradients. While this approach effectively performs the attention computation twice (once forward, once backward), the reduction in HBM read\/write operations is so massive that the overall wall-clock time decreases. This validates the central tenet of IO-awareness: on modern hardware, compute is cheap and abundant, while memory bandwidth is expensive and scarce.<\/span>1<\/span><\/p>\n <\/p>\n
3.4 IO Complexity Analysis<\/b><\/h3>\n
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The theoretical rigor of FlashAttention is established through an analysis of IO complexity. The authors prove that the number of HBM accesses for FlashAttention is $O(N^2 d^2 M^{-1})$, where $M$ is the size of the SRAM and $d$ is the head dimension. In contrast, standard attention requires $\\Omega(Nd + N^2)$ accesses.<\/span><\/p>\nThis formula $O(N^2 d^2 M^{-1})$ reveals a critical insight: the efficiency of the algorithm is inversely proportional to the size of the SRAM. A larger SRAM allows for larger tiles, which essentially allows the algorithm to amortize the cost of loading $Q$ across a larger number of $K, V$ interactions. The analysis demonstrates that FlashAttention is asymptotically optimal with respect to memory movement for exact attention across the memory hierarchy.<\/span>2<\/span><\/p>\n4. FlashAttention-2: Optimizing Parallelism and Work Partitioning<\/b><\/h2>\n
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While FlashAttention-1 successfully solved the memory IO bottleneck, strictly monitoring memory movement revealed a secondary inefficiency: compute utilization. Benchmarks indicated that FlashAttention-1 achieved only 25-40% of the theoretical peak FLOPs on A100 GPUs. The Tensor Cores were often waiting for non-matrix operations or suffering from suboptimal thread scheduling. FlashAttention-2 (v2) was engineered to address these computational inefficiencies by restructuring the algorithm\u2019s parallelism and reducing non-matrix-multiply overheads.<\/span>5<\/span><\/p>\n <\/p>\n
4.1 Parallelism Across Sequence Length<\/b><\/h3>\n
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The most significant architectural shift in FlashAttention-2 is the parallelization scheme. FlashAttention-1 parallelized primarily over the <\/span>batch size<\/b> and the <\/span>number of heads<\/b>. Each thread block (Streaming Multiprocessor or SM) was assigned a specific attention head for a specific sample in the batch.<\/span><\/p>\nWhile effective for training with large batch sizes, this approach creates <\/span>low occupancy<\/b> (idle compute cores) in two critical scenarios:<\/span><\/p>\n\n- Small Batch Sizes:<\/b> Common during inference or fine-tuning.<\/span><\/li>\n
- Long Contexts:<\/b> If the sequence length is massive but the batch size is 1, a GPU with 108 SMs (like an A100) might only utilize a fraction of its cores if the number of heads is small.<\/span><\/li>\n<\/ol>\n
FlashAttention-2 introduces <\/span>Sequence Parallelism<\/b> to the kernel. It partitions the sequence length dimension itself. The outer loop of the algorithm is now parallelized such that different thread blocks process different chunks of the Query sequence. This ensures that even with a batch size of 1, the massive computational work of a long sequence can be distributed across all available SMs on the GPU. This change significantly boosts throughput for long-context workloads and is a prerequisite for efficient inference of modern LLMs.<\/span>6<\/span><\/p>\n <\/p>\n
4.2 Work Partitioning and Loop Ordering<\/b><\/h3>\n
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FlashAttention-2 also inverts the loop structure of the block computation.<\/span><\/p>\n\n- v1 Structure:<\/b> The outer loop iterates over $K, V$ blocks, and the inner loop iterates over $Q$. This required writing partial results of $O$ to HBM and accumulating them, which introduced overhead and numerical precision complexities.<\/span><\/li>\n
- v2 Structure:<\/b> The outer loop iterates over $Q$ blocks, and the inner loop iterates over $K, V$. This allows the output block $O_i$ to be maintained in registers\/SRAM throughout the entire computation of its attention over all keys and values. $O_i$ is only written to HBM once it is fully computed.<\/span><\/li>\n<\/ul>\n
This restructuring simplifies the logic for updating the online softmax statistics and eliminates the need for intermediate HBM writes for partial accumulators, further reducing IO traffic.<\/span>5<\/span><\/p>\n <\/p>\n
4.3 Reducing Non-Matmul FLOPs<\/b><\/h3>\n
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In the attention computation, matrix multiplications (GEMMs) are executed by specialized Tensor Cores, which offer immense throughput. However, auxiliary operations\u2014Softmax, Exponentials, Division, and scalar updates\u2014are executed by the Multi-Function Units (SFUs) or standard CUDA cores, which are significantly slower (often by a factor of 16x or more).<\/span><\/p>\nIn FlashAttention-1, the iterative update of the online softmax statistics required frequent rescaling of the accumulator vectors. This rescaling is a vector-scalar multiplication that runs on the slower units. FlashAttention-2 optimizes the mathematics of the online softmax to delay these rescaling operations. By keeping track of unnormalized attention scores and applying the normalization only at the very end of the loop, v2 minimizes the workload on the SFUs. This allows the GPU to dedicate more cycles to the high-throughput Tensor Core GEMMs, pushing utilization closer to the theoretical limit.<\/span>6<\/span><\/p>\n <\/p>\n
4.4 Warp-Level Optimization<\/b><\/h3>\n
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FlashAttention-2 delves deep into the thread hierarchy of the GPU. It optimizes how work is distributed among “warps” (groups of 32 threads). By refining the data layout in shared memory to avoid “bank conflicts” (where multiple threads try to access the same memory bank simultaneously) and minimizing synchronization barriers between warps, FlashAttention-2 reduces the latency of the inner loop. The result is a 2x speedup over v1, reaching up to <\/span>225 TFLOPS<\/b> on A100 GPUs for the backward pass, which corresponds to roughly 72% of the model’s theoretical FLOP utilization.<\/span>6<\/span><\/p>\n <\/p>\n
4.5 Feature Parity and Extensions<\/b><\/h3>\n
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Beyond raw speed, FlashAttention-2 expanded support for critical Transformer features:<\/span><\/p>\n\n- Head Dimensions:<\/b> Support extended up to 256, accommodating larger models.<\/span>7<\/span><\/li>\n
- ALiBi:<\/b> Native support for Attention with Linear Biases, crucial for extrapolation.<\/span>9<\/span><\/li>\n
- Sliding Window Attention (SWA):<\/b> Optimized kernels for local attention windows (e.g., Mistral 7B), which enforce a sparsity pattern where tokens only attend to a local neighborhood.<\/span>9<\/span><\/li>\n
- Paged KV Cache:<\/b> Integration with PagedAttention concepts for efficient inference memory management.<\/span>9<\/span><\/li>\n<\/ul>\n
5. FlashAttention-3: Asynchrony and Hopper-Specific Specialization<\/b><\/h2>\n
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As hardware evolves, software must adapt. The release of NVIDIA’s <\/span>Hopper architecture (H100)<\/b> marked a significant shift in GPU design, introducing powerful new asynchronous hardware primitives. FlashAttention-2, designed primarily for the synchronous execution model of the Ampere (A100) generation, could not fully exploit these features, achieving only ~35% utilization on H100s. FlashAttention-3 was engineered specifically to bridge this gap, leveraging asynchrony to hide memory latency completely.<\/span>5<\/span><\/p>\n <\/p>\n
5.1 New Hardware Primitives: WGMMA and TMA<\/b><\/h3>\n
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To understand FlashAttention-3, one must understand the Hopper-specific instructions it utilizes:<\/span><\/p>\n\n- WGMMA (Warpgroup Matrix Multiply-Accumulate):<\/b> A new instruction that allows a group of warps (a “warpgroup,” consisting of 128 threads) to perform matrix multiplication cooperatively. Crucially, WGMMA is <\/span>asynchronous<\/b>\u2014the instruction is issued, and the Tensor Cores begin execution, but the CPU thread (warp scheduler) does not block. It is free to execute other non-dependent instructions immediately.<\/span><\/li>\n
- TMA (Tensor Memory Accelerator):<\/b> A specialized hardware unit dedicated to copying data between global memory (HBM) and shared memory (SRAM). In previous architectures, threads had to manually issue load instructions. With TMA, the program issues a copy command, and this dedicated unit handles the entire transfer asynchronously, freeing up the threads to do math.<\/span><\/li>\n<\/ol>\n
FlashAttention-3 is built entirely around maximizing the overlap between these two units.<\/span>12<\/span><\/p>\n <\/p>\n
5.2 Producer-Consumer Asynchrony and Warp Specialization<\/b><\/h3>\n
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The defining characteristic of FlashAttention-3 is its use of <\/span>Warp Specialization<\/b>. In previous versions, all warps in a thread block performed the same sequence of tasks: load data $\\rightarrow$ wait $\\rightarrow$ compute $\\rightarrow$ wait. In FlashAttention-3, warps are specialized into distinct roles:<\/span><\/p>\n\n- Producer Warps:<\/b> These warps are responsible solely for issuing TMA instructions to bulk-load data from HBM to shared memory. They act as the “feeders.”<\/span><\/li>\n
- Consumer Warps:<\/b> These warps execute the WGMMA instructions and Softmax operations. They act as the “eaters.”<\/span><\/li>\n<\/ul>\n
This separation allows for a “Ping-Pong” or circular buffering strategy. While the consumer warps are crunching numbers on the Tensor Cores for <\/span>Block $i$<\/span><\/i>, the producer warps are already pre-fetching <\/span>Block $i+1$<\/span><\/i> via the TMA. The use of hardware barriers (mbarriers) ensures synchronization only when absolutely necessary. This asynchronous pipeline effectively hides the latency of memory access, ensuring that the Tensor Cores are never starved of data.<\/span>13<\/span><\/p>\n <\/p>\n
5.3 Overlapping GEMM and Softmax<\/b><\/h3>\n
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A major bottleneck in attention is the sequential dependency between the GEMM (computing $S = QK^T$) and the Softmax ($P = \\text{softmax}(S)$). Mathematically, you cannot calculate the Softmax until the GEMM is finished. In a synchronous execution model, this leaves the Tensor Cores idle while the Softmax runs on the Multi-Function Units.<\/span><\/p>\nFlashAttention-3 breaks this dependency using the asynchronous nature of WGMMA. The algorithm schedules the <\/span>Softmax of the previous block<\/b> to run concurrently with the <\/span>GEMM of the current block<\/b>.<\/span><\/p>\n\n- Cycle N:<\/span><\/i> Issue WGMMA for Block $K_{j+1}$. (Tensor Cores busy).<\/span><\/li>\n
- Cycle N (Concurrent):<\/span><\/i> Compute Softmax for Block $K_j$. (SFUs busy).<\/span><\/li>\n<\/ul>\n
This interleaving of operations ensures that both the Tensor Cores and the SFUs are kept active simultaneously, maximizing the total throughput of the SM.<\/span>5<\/span><\/p>\n <\/p>\n
5.4 Low-Precision FP8 Support via Incoherent Processing<\/b><\/h3>\n
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FlashAttention-3 natively supports <\/span>FP8 (8-bit Floating Point)<\/b> computation, a feature introduced in Hopper to theoretically double peak throughput compared to FP16. However, implementing attention in FP8 is non-trivial due to the non-linear Softmax operation. Softmax is highly sensitive to outliers; a single large value in $S$ can push the exponents into ranges that FP8 cannot represent, leading to severe quantization errors and model collapse.<\/span><\/p>\nFlashAttention-3 solves this with Incoherent Processing utilizing the Hadamard Transform. Before quantization, the algorithm multiplies the Query and Key matrices by a random orthogonal matrix (often a Randomized Hadamard Transform). This mathematical operation effectively “rotates” the vector space. It “smears” or redistributes outlier values across multiple dimensions without changing the dot product results (since the transform is orthogonal).<\/span><\/p>\n <\/p>\n
$$(QM)(KM)^T = Q M M^T K^T = Q I K^T = QK^T$$<\/span><\/p>\n <\/p>\n
This transformation prevents any single entry from dominating the quantization range. FlashAttention-3 also employs Block Quantization, where different scaling factors are used for different blocks of the matrix. Together, these techniques allow FlashAttention-3 to achieve near-FP16 accuracy with FP8 speed, reaching up to 1.2 PFLOPS on H100 GPUs.11<\/span><\/p>\n <\/p>\n
5.5 Performance Comparison of Generations<\/b><\/h3>\n
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The evolution of FlashAttention demonstrates a clear trajectory of increasing hardware utilization.<\/span><\/p>\n <\/p>\n
\n\n\n| Feature<\/b><\/td>\n | FlashAttention-1<\/b><\/td>\n | FlashAttention-2<\/b><\/td>\n | FlashAttention-3<\/b><\/td>\n<\/tr>\n\n| Release Era<\/b><\/td>\n | 2022<\/span><\/td>\n | 2023<\/span><\/td>\n | 2024 (Beta)<\/span><\/td>\n<\/tr>\n\n| Core Concept<\/b><\/td>\n | Tiling, Recomputation<\/span><\/td>\n | Sequence Parallelism<\/span><\/td>\n | Asynchrony, Warp Specialization<\/span><\/td>\n<\/tr>\n\n| Parallelism<\/b><\/td>\n | Batch, Heads<\/span><\/td>\n | Batch, Heads, Sequence<\/span><\/td>\n | Batch, Heads, Sequence, Warpgroup<\/span><\/td>\n<\/tr>\n\n| GPU Optimization<\/b><\/td>\n | SRAM Caching<\/span><\/td>\n | Reduced Non-Matmul FLOPs<\/span><\/td>\n | WGMMA, TMA, Overlap<\/span><\/td>\n<\/tr>\n\n| Architecture Target<\/b><\/td>\n | Ampere (A100)<\/span><\/td>\n | Ampere (A100)<\/span><\/td>\n | Hopper (H100)<\/span><\/td>\n<\/tr>\n | | | | | |
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