Shared memory distinguishes itself from traditional CPU caches by offering deterministic latency and explicit programmer control. Located physically within each Streaming Multiprocessor (SM), it enables low-latency data reuse and efficient inter-thread communication within a Thread Block or Cooperative Thread Array (CTA).<\/span>3<\/span> However, the architectural implementation of shared memory introduces a complex set of constraints, most notably the system of memory <\/span>banks<\/b>. The performance of a CUDA kernel is frequently dictated not by the raw floating-point capability of the hardware, but by the developer’s ability to navigate the intricacies of bank access patterns.<\/span><\/p>\n When multiple threads within a warp (the fundamental unit of execution in CUDA, comprising 32 threads) attempt to access different memory addresses that map to the same physical bank during a single cycle, a <\/span>bank conflict<\/b> occurs.<\/span>5<\/span> The hardware must serialize these conflicting accesses, reducing the effective bandwidth by a factor proportional to the degree of conflict. As architectures have evolved from Fermi to the modern Hopper H100, the mechanisms for handling shared memory have grown in sophistication, introducing features such as configurable bank widths, asynchronous copy instructions (cp.async), and the Tensor Memory Accelerator (TMA).<\/span>7<\/span><\/p>\n This report provides an exhaustive examination of CUDA shared memory architecture. It dissects the microarchitectural mechanics of bank conflicts, explores the mathematical foundations of conflict-free access patterns, and details advanced optimization strategies ranging from algorithmic padding to hardware-accelerated swizzling. Furthermore, it integrates profiling methodologies using NVIDIA Nsight Compute to provide a verifiable, data-driven approach to optimization.<\/span><\/p>\n To master shared memory optimization, one must first deconstruct its physical organization. Unlike global memory, which is accessed via a sophisticated cache hierarchy (L1\/L2) and memory controllers, shared memory is a direct-access SRAM (Static Random Access Memory) structure located on the SM die.<\/span><\/p>\n The fundamental unit of bandwidth scaling in shared memory is the <\/span>bank<\/b>. Rather than being a monolithic block of memory where only one access can occur at a time, shared memory is divided into equally sized modules that can function independently.<\/span><\/p>\n Across all modern NVIDIA architectures\u2014from Maxwell (Compute Capability 5.x) through Pascal, Volta, Ampere, and Hopper (Compute Capability 9.0)\u2014shared memory is organized into <\/span>32 banks<\/b>.<\/span>9<\/span> This number is not arbitrary; it corresponds exactly to the number of threads in a standard CUDA warp (32 threads).<\/span><\/p>\n This 1:1 correspondence is the architectural ideal: in a perfectly optimized scenario, every thread in a warp issues a memory request to a unique bank. If this condition is met, the memory subsystem can service all 32 requests simultaneously in a single clock cycle, achieving maximum theoretical bandwidth.<\/span>10<\/span><\/p>\n Each bank has a width of <\/span>4 bytes (32 bits)<\/b>.<\/span>6<\/span> This means that inside a single bank, data is stored in successive 32-bit words. The implication for bandwidth is significant:<\/span><\/p>\n It is crucial to note the distinction between “bandwidth” and “latency.” Shared memory latency is roughly 20-30 cycles (comparable to L1 cache), whereas global memory latency can exceed 400 cycles.<\/span>16<\/span> While the latency is low, the <\/span>throughput<\/span><\/i> (bandwidth) is limited by bank parallelism. If bank conflicts occur, the effective bandwidth drops precipitously, potentially starving the CUDA Cores or Tensor Cores waiting for data.<\/span><\/p>\n The system determines which bank holds a specific byte address using a modulo mapping scheme. This is often referred to as “word interleaving.”<\/span><\/p>\n For the standard 32-bit mode, the bank index for a given byte address $A$ is calculated as:<\/span><\/p>\n <\/p>\n $$\\text{Bank Index} = \\left( \\frac{A}{4} \\right) \\pmod{32}$$<\/span><\/p>\n This formula implies that successive 32-bit words are assigned to successive banks in a round-robin fashion.<\/span>13<\/span><\/p>\n This interleaved layout is designed to optimize linear access patterns. If a warp reads a contiguous array of float or int values (e.g., Thread[i] reads Array[i]), the addresses naturally stride across the banks. Thread 0 accesses Bank 0, Thread 1 accesses Bank 1, and so on, resulting in a conflict-free transaction.<\/span><\/p>\n While modern architectures have standardized on 4-byte banks, it is informative to acknowledge that the Kepler architecture (Compute Capability 3.x) introduced a configurable bank width feature. Developers could use cudaDeviceSetSharedMemConfig() to toggle between 4-byte and 8-byte bank modes.<\/span>3<\/span> The 8-byte mode was intended to optimize double-precision (64-bit) workloads by allowing a single bank to deliver 64 bits per cycle.<\/span><\/p>\n2. Architectural Fundamentals of Shared Memory<\/b><\/h2>\n
2.1 Physical Organization and Bank Structure<\/b><\/h3>\n
2.1.1 The 32-Bank Standard<\/b><\/h4>\n
2.1.2 Bank Width and Bandwidth<\/b><\/h4>\n
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2.2 Address Mapping and Interleaving Logic<\/b><\/h3>\n
2.2.1 The Mapping Formula<\/b><\/h4>\n
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2.2.2 Historical Context: Configurable Bank Widths<\/b><\/h4>\n
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