Section 1: The Inevitable End of the FinFET Scaling Roadmap
The FinFET architecture represented a monumental leap in semiconductor technology, enabling the industry to overcome the fundamental scaling barriers of traditional planar transistors and continue the relentless pace of Moore’s Law for over a decade.1 By extruding the transistor channel into a three-dimensional “fin,” the gate was able to exert control from three sides, dramatically improving electrostatic integrity and suppressing the short-channel effects that had plagued sub-28nm planar devices.2 This innovation became the dominant transistor design for the 14nm, 10nm, and 7nm process nodes, powering a generation of advanced computing.4 However, as the industry pushes into the sub-5nm domain, the very principles that made the FinFET successful have become its primary limitations. The architecture is now confronting a confluence of physical, electrical, and manufacturing challenges that signal a point of diminishing returns, making a transition to a new device structure not just beneficial, but imperative.
bundle-multi-3-in-1—sap-mm By Uplatz
1.1 The Physics of Diminishing Returns: Degradation of Electrostatic Control
The foundational advantage of the FinFET over its planar predecessor was its superior gate control. With the gate wrapping the channel on three of four sides, it could more effectively modulate the flow of charge carriers and “choke off” the channel in the off-state.2 This principle, however, begins to fail at the atomic scales of 5nm and below. The core issue is that the gate lacks control over the bottom of the fin, where it is anchored to the substrate. As other device dimensions shrink, this uncontrolled region becomes a significant leakage path.2
At these advanced nodes, quantum mechanical effects, such as direct source-to-drain tunneling, become increasingly pronounced, leading to a substantial rise in off-state leakage current ($I_{off}$).5 This leakage compromises the transistor’s ability to maintain a definitive “off” state, a critical requirement for low-power operation. The diminished gate control also leads to a resurgence of the very short-channel effects (SCEs) that FinFETs were designed to solve. Phenomena such as drain-induced barrier lowering (DIBL), where the drain voltage undesirably influences the channel, and a degradation of the subthreshold swing ($SS$), which measures how effectively a transistor can switch from off to on, become severe once again.5 While the 3D structure provided a temporary reprieve, the fundamental physics of a partially controlled channel reassert themselves as the gate length shrinks towards single-digit nanometers, signaling the electrostatic limit of the tri-gate architecture.6
1.2 Manufacturing at the Limit: The Tall Fin Conundrum and Parasitic Penalties
The physical scaling of logic cells in advanced nodes has created a manufacturing deadlock for the FinFET architecture. To continue increasing transistor density, the footprint of each standard cell must shrink. This forces a reduction in the number of fins per transistor, often down to a single fin for nFETs and pFETs in the most advanced designs.7 To compensate for the loss of effective channel width ($W_{eff}$) from removing fins and thereby maintain the necessary drive current ($I_{on}$), designers are forced to make this single fin progressively taller and thinner.7
This “tall fin” approach, however, introduces a cascade of new and often more severe problems. From a manufacturing perspective, fabricating extremely tall, thin, and uniform fins with high aspect ratios is a formidable challenge. It requires highly sophisticated and expensive lithography and etching processes, often involving multi-patterning techniques like self-aligned quadruple patterning (SAQP), which significantly increase production costs and cycle times.2 These tall structures are also mechanically fragile and susceptible to damage from the high-stress films used for mobility enhancement.2 Furthermore, the etching process is never perfect, resulting in fin profiles that are not perfectly vertical, leading to performance variability and persistent leakage paths at the fin’s base.7
Even if a perfect tall fin could be manufactured, it creates a crippling electrical engineering problem. As the fin grows taller, parasitic capacitance and resistance increase dramatically.5 The contact resistance between the metal interconnects and the semiconductor also becomes proportionally larger relative to the channel resistance, creating a performance bottleneck.5 These parasitic effects degrade the transistor’s switching speed and power efficiency, effectively erasing the gains achieved through dimensional scaling. For instance, a single 100 nm tall fin is not equivalent in performance to two adjacent 50 nm fins due to the accumulation of these parasitic penalties.7 This dynamic creates a vicious cycle: the geometric solution for area scaling (a tall, single fin) directly worsens the device’s electrical performance and manufacturability, leading to a technological dead end where further scaling provides no net benefit.
The industry’s progression illustrates a fundamental shift in the nature of semiconductor scaling. For decades, the primary obstacle was lithography—the ability to print ever-smaller features. The end of the FinFET era, however, signifies a move from a lithography-limited regime to an architecture-limited one. While advanced lithography like Extreme Ultraviolet (EUV) remains a critical enabler, the primary bottleneck is now the inherent geometry of the transistor itself. The physical and electrical flaws of a partially-gated fin structure are the limiting factor, regardless of how small it can be patterned. This realization is the strategic driver behind the industry’s massive investment in a complete architectural transition to Gate-All-Around, a move deemed necessary because no amount of refinement to the FinFET design can solve its fundamental geometric shortcomings.
1.3 The Quantization Problem: A Loss of Design Flexibility
A more subtle but equally significant limitation of the FinFET architecture is the quantization of its channel width. In a planar transistor, a designer can specify the channel width as a continuous variable, allowing for fine-grained optimization of transistor strength to meet specific power and performance targets. In a FinFET, however, the effective channel width is an integer multiple of the width of a single fin.2 This finite granularity imposes a rigid constraint on circuit designers.
This lack of continuous control over transistor width and the limited freedom in channel length for a given architecture result in a large number of Restricted Design Rules (RDRs).2 These rules are necessary to manage the variability of the complex 3D etching processes but they severely complicate the optimization of both digital and analog circuits. For high-performance digital logic, designers may be forced to use more fins than optimal, wasting area and power. For sensitive analog circuits, where precise transistor matching and sizing are critical, the quantized nature of the fin makes achieving desired performance characteristics exceptionally difficult. This loss of design flexibility forces engineers into suboptimal compromises, preventing them from extracting the full potential from a given technology node and serving as another critical driver for a new architecture that restores this essential degree of freedom.
Section 2: The Gate-All-Around Paradigm: A Fundamental Reinvention of the Transistor
In response to the fundamental limitations of the FinFET, the semiconductor industry is transitioning to the Gate-All-Around (GAA) architecture. This new paradigm is not merely an incremental improvement but a comprehensive reinvention of the transistor, designed specifically to solve the electrostatic, manufacturing, and design challenges that have stalled FinFET scaling. By fundamentally changing the geometry of the gate-channel interface, GAA technology re-ignites the path toward higher performance, lower power, and greater density, positioning it as the foundational architecture for the 3nm node and beyond.10
2.1 Maximizing Electrostatic Integrity: The Power of 360-Degree Control
The defining characteristic and principal advantage of a GAA transistor is that the gate material completely envelops the channel on all four sides.11 This 360-degree gate control provides a uniform, powerful electric field that can modulate the entire volume of the channel, achieving what is considered near-perfect electrostatic integrity.14
This complete envelopment directly addresses the primary weakness of the FinFET. By eliminating the uncontrolled bottom channel region, the GAA structure allows the gate to “choke off” current flow much more effectively when the transistor is in the off-state. This results in a dramatic reduction in leakage current and provides superior mitigation of short-channel effects like DIBL and subthreshold swing degradation, even at extremely short gate lengths.3 This enhanced electrostatic control is the key physical enabler for continued transistor scaling, allowing for the miniaturization of devices beyond the 3nm node without the crippling leakage penalties that plague advanced FinFETs.11 The GAA architecture can thus be seen as the logical conclusion of the multi-gate transistor evolution that began with the tri-gate FinFET, achieving the ideal gate-channel geometry for maximum control.
| Feature | Planar MOSFET | FinFET | Gate-All-Around (GAA) FET |
| Gate Control | 1-sided (Top Gate) | 3-sided (Tri-Gate) | 4-sided (All-Around Gate) |
| Channel Geometry | Horizontal, planar channel | Vertical, 3D “fin” | Horizontal, suspended “nanosheets” or “nanowires” |
| Primary Scaling Mechanism | Gate length reduction | Fin height increase, fin pitch reduction | Vertical stacking of channels, nanosheet width tuning |
| Electrostatic Integrity | Poor, susceptible to SCEs | Good, improved control over channel | Excellent, near-ideal control over entire channel volume |
| Short-Channel Effect Mitigation | Limited | Significant reduction compared to planar | Superior mitigation, enabling sub-3nm scaling |
| Drive Current per Footprint | Baseline | High | Very High (due to stacking and wider effective channels) |
| Design Flexibility (Channel Width) | Continuous | Quantized (integer number of fins) | Continuous (tunable nanosheet width) |
| Key Manufacturing Challenge | Doping control, lithography | High-aspect-ratio fin etch, uniformity | Selective etch for channel release, inner spacer formation |
2.2 From Vertical Fins to Horizontal Sheets: A New Dimension in Density and Performance
The GAA architecture introduces a revolutionary change in how transistor channels are constructed. Instead of extruding vertical fins from the substrate, GAA enables the creation of horizontally oriented, suspended channels that are stacked vertically.13 These channels can be shaped as either thin nanowires or wider, ribbon-like nanosheets.
This vertical stacking capability is a game-changer for performance and density. By placing multiple current-carrying channels on top of one another, GAA can significantly increase the total effective channel width ($W_{eff}$) within the exact same layout footprint.13 A larger $W_{eff}$ directly translates to a higher drive current ($I_{on}$), which boosts transistor performance without consuming more chip area.14 This approach elegantly solves the “tall fin conundrum” that plagues FinFETs. Instead of making a single, tall fin that is difficult to manufacture and suffers from high parasitic capacitance, GAA achieves higher performance by adding parallel channels in the vertical dimension—a far more efficient and scalable method. This architectural innovation provides a new vector for performance scaling, breaking the deadlock encountered at the end of the FinFET roadmap.
2.3 Quantifying the PPA Advantage: The Business Case for GAA
The architectural superiority of GAA translates into tangible and compelling improvements in the key industry metrics of Power, Performance, and Area (PPA). These gains form the business case that justifies the immense capital investment and R&D effort required for the industry-wide transition.
Leading foundries have published impressive targets for their GAA-based nodes. Samsung, the first to introduce GAA at its 3nm node, claims that its initial process offers up to a 50% reduction in power consumption, a 30% increase in performance, or a 35% decrease in area when compared to its 5nm FinFET technology.17 TSMC, which is introducing GAA at its 2nm (N2) node, is targeting a 10-15% performance improvement or a 25-30% power reduction relative to its most advanced 3nm FinFET (N3E) process.19 These significant PPA gains are essential for next-generation products in the most demanding market segments, including high-performance computing (HPC), artificial intelligence (AI) accelerators, and advanced mobile processors.7
Beyond the raw performance numbers, the GAA architecture provides a crucial, though less obvious, advantage: it restores the design flexibility that was lost in the FinFET era. The quantization of fin width was a major constraint for circuit designers.2 The nanosheet variant of GAA resolves this by reintroducing a “continuous” variable for channel width. Designers can tune the physical width of the nanosheets themselves, allowing for fine-grained control over transistor strength.16 This capability is a powerful enabler for Design Technology Co-Optimization (DTCO), a methodology where the manufacturing process and the circuit design are developed in tandem to achieve the optimal PPA for a specific application.18 This restored flexibility allows engineers to build more efficient and highly optimized circuits.
Consequently, GAA should be viewed not as a single, monolithic device but as a flexible and versatile technology platform. A single GAA process can be used to fabricate transistors with different characteristics on the same die: wide nanosheets for high-speed CPU cores, narrower nanosheets for power-efficient logic blocks, and perhaps even nanowires for ultra-low-leakage applications like keep-alive circuits.16 This adaptability makes GAA a more future-proof architecture, capable of serving the diverse requirements of a wide range of products, from massive data center chips to tiny, power-sipping Internet of Things (IoT) devices.20
Section 3: Architectural Divergence: Nanosheet vs. Nanowire FETs
While Gate-All-Around defines the overarching principle of 360-degree gate control, its implementation is not monolithic. The two primary variants of GAA transistors are the Nanosheet FET (NSFET) and the Nanowire FET (NWFET). Though they share the same fundamental operating principle, their distinct channel geometries lead to different electrical characteristics and performance trade-offs. The choice between them is not arbitrary but is a critical engineering decision that depends on the specific PPA goals of the application, positioning them as distinct solutions for different segments of a chip design.16
3.1 Structural and Electrical Comparison: The Geometry of Performance
The fundamental structural difference between the two architectures lies in the cross-sectional shape of the current-carrying channel. A Nanowire FET features a channel with a nearly square or circular cross-section, where the width and thickness are approximately equal.22 In contrast, a Nanosheet FET employs a channel that is significantly wider than it is thick, creating a flat, ribbon-like structure.22
This seemingly simple geometric distinction has profound consequences for device performance. The primary advantage of the nanosheet structure is its ability to provide a much larger effective channel width ($W_{eff}$) within a given layout footprint compared to a nanowire.16 This larger effective width allows the NSFET to carry a significantly higher drive current ($I_{on}$), resulting in superior DC performance and faster switching speeds.16 Technology Computer-Aided Design (TCAD) simulations have confirmed that this performance advantage stems from an enhanced volume inversion effect within the wider channel and a more favorable subband occupation, which leads to a higher carrier injection velocity.16 This makes the Nanosheet the clear architectural choice for maximizing performance.
3.2 Application-Specific Optimization: High-Performance vs. Low-Power
The distinct electrical profiles of NSFETs and NWFETs make them naturally suited for different types of applications.
- Nanosheet FETs for High Performance: With their superior drive current and DC performance, NSFETs are the ideal choice for standard-performance (SP) and high-performance (HP) applications.22 Logic circuits in CPUs, GPUs, and AI accelerators, where maximizing computational throughput is the primary goal, benefit directly from the high current delivery of the wide nanosheet channels. The ability to tune the width of the nanosheet provides an additional lever for designers to optimize performance, with wider sheets used for the most critical, speed-sensitive paths on a chip.16
- Nanowire FETs for Low Power: Conversely, Nanowire FETs exhibit superior short-channel characteristics due to their excellent two-dimensional structural confinement.22 The gate’s control over the smaller, more confined channel volume is extremely effective at minimizing leakage current. This makes NWFETs the better-performing architecture for low-power (LP) applications where energy efficiency and minimizing static power consumption are more critical than raw speed.22 This could include circuits for IoT devices, wearable technology, or specific low-power blocks within a larger System-on-Chip (SoC).
This divergence has led the industry to largely focus on the nanosheet architecture as the mainstream workhorse for next-generation technology nodes. The primary economic driver for node transitions is the demand for higher performance in flagship products like server CPUs and mobile application processors, which are best served by NSFETs.16 Consequently, the branded GAA technologies from major foundries—such as Samsung’s MBCFET™, Intel’s RibbonFET, and TSMC’s Nanosheet—are all based on the nanosheet/ribbon concept.18 The Nanowire, while technologically significant, is thus positioned more as a specialized solution for niche, ultra-low-power markets or for specific IP blocks on a die where leakage is the dominant concern.
| Feature | Nanosheet FET (NSFET) | Nanowire FET (NWFET) |
| Channel Cross-Section | Rectangular (Wide, Thin Ribbon) | Square or Circular (Width ≈ Thickness) |
| Effective Channel Width ($W_{eff}$) | High, tunable by design | Lower, fixed by wire dimensions |
| Primary Application | High-Performance (HP) & Standard-Performance (SP) Computing | Low-Power (LP) & Ultra-Low-Leakage Applications |
| Drive Current ($I_{on}$) | Superior; higher due to larger $W_{eff}$ and enhanced volume inversion | Lower |
| Short-Channel Control | Excellent | Excellent; superior 2D structural confinement |
| Suitability for Low Power | Good; can be optimized with narrow sheets | Superior; excellent leakage control |
| Susceptibility to TID Effects | Higher; larger gate oxide area and corners create more trap sites | Lower; smaller surface area and more uniform gate control |
| Key Advantage | High performance and design flexibility (tunable width) | Ultra-low leakage and superior radiation hardness |
3.3 Secondary Performance Characteristics: A Deeper Look at Reliability
Beyond the primary metrics of performance and power, a deeper analysis reveals other critical differences, particularly in reliability. A study analyzing the effects of Total Ionizing Dose (TID) radiation on both architectures found that NSFETs are significantly more vulnerable to radiation-induced performance degradation than NWFETs.25
The reason for this discrepancy is again rooted in geometry. The NSFET, with its wider channel, inherently has a larger gate oxide surface area and a longer channel circumference. This provides more physical locations for radiation-induced hole traps to form at the silicon-dielectric interface, leading to larger shifts in the transistor’s threshold voltage ($V_T$).25 Furthermore, the corners of the rectangular nanosheet structure are points of weaker electrostatic control compared to the flat regions. These corners were found to generate approximately 30% more interface traps, making them particularly susceptible to TID effects.25 In contrast, the more uniform geometry of the nanowire results in fewer trap sites and better overall radiation tolerance.
This creates a fundamental, physics-based trade-off between performance and reliability. The very geometric features that give the NSFET its high drive current—the wide surface area and long circumference—are the same features that make it a larger target for radiation damage. This implies that for applications in harsh environments, such as aerospace, defense, satellite communications, or high-reliability medical implants, designers may be forced to choose the lower-performance NWFET architecture to ensure operational robustness. Alternatively, they would need to implement complex and area-intensive radiation-hardening-by-design (RHBD) techniques to mitigate the inherent vulnerabilities of the NSFET. This highlights that the “best” GAA architecture is not universal, but is highly dependent on the specific operational context and reliability requirements of the end product.
Section 4: The Gauntlet of High-Volume Manufacturing
The theoretical advantages of the Gate-All-Around architecture can only be realized through the successful development of an extraordinarily complex and precise manufacturing process. The transition from FinFET to GAA represents one of the most significant shifts in fabrication technology in decades, introducing a host of novel materials, process steps, and metrology challenges that push the boundaries of materials science and chemical engineering.26 While EUV lithography remains a critical enabler for patterning, the success of a GAA process hinges more on the atomic-level control of deposition and etching of different materials in a complex 3D structure.10
4.1 The Epitaxial Foundation: Building the Superlattice
The GAA fabrication flow begins with a step that has no direct equivalent in a standard FinFET process: the epitaxial growth of a multi-layer “superlattice” stack.13 This process involves depositing alternating, ultra-thin layers of silicon (Si) and a sacrificial material, typically silicon-germanium (SiGe), onto the substrate. This Si/SiGe heterostructure is the foundation from which the transistor channels will be formed.13
The precision required in this step is paramount. The thickness of the Si layers will define the thickness of the final nanosheet channels, while the thickness of the SiGe layers will determine the vertical spacing between them. Any variation in the thickness, composition, or crystal quality of these layers will translate directly into variability in the performance and power consumption of the final transistors.27 Achieving angstrom-level uniformity across a 300 mm wafer for a stack that may contain multiple pairs of these layers requires unprecedented control over epitaxial growth reactors and processes. After the superlattice is grown, it is patterned into pillars, which are geometrically analogous to the fins in a FinFET process.13
4.2 Channel Release and Inner Spacer Formation: The Heart of the GAA Process
The most unique, innovative, and challenging module in GAA manufacturing is the “channel release” sequence. This is where the suspended nanosheets are created. The process involves several delicate steps:
- Inner Spacer Definition: First, an indentation is carefully etched into the sides of the SiGe layers within the patterned pillar. This step is critical as it defines the gate length and creates the physical space for a crucial component known as the inner spacer.13
- Selective Etching: Next, a highly selective chemical etch is used to remove the sacrificial SiGe layers from between the Si layers. This must be accomplished without damaging or even slightly etching the extremely thin silicon nanosheets.16 This leaves the silicon channels suspended in space, held only at the source and drain ends. Achieving perfect selectivity is a profound chemical engineering challenge, as the etchant must distinguish between two very similar semiconductor materials at an atomic level.
- Inner Spacer Deposition: The cavities created by the removal of the SiGe are then filled with a dielectric material to form the inner spacers. These spacers are essential for electrically isolating the eventual gate metal from the source and drain regions, thereby minimizing parasitic gate-to-source/drain capacitance ($C_{gs}$ and $C_{gd}$).13 Minimizing this parasitic capacitance is a key factor in unlocking the high-speed performance potential of GAA transistors.
This entire module is performed on fragile, suspended structures and involves a sequence of highly controlled deposition and removal steps that have no precedent in high-volume FinFET manufacturing.
4.3 Atomic-Scale Metrology and Process Control: Seeing the Invisible
The intricate, three-dimensional, and often buried structures of GAA transistors render traditional manufacturing metrology techniques insufficient. The need to measure and control features with sub-nanometer accuracy has forced a revolution in process control and inspection.10
Standard optical inspection and top-down critical dimension scanning electron microscopy (CD-SEM) cannot resolve or even “see” many of the most critical parameters, such as the thickness of the suspended nanosheets, the uniformity of the inner spacer, or the conformity of the gate metal under the sheets.26 To overcome this, fabs must deploy a suite of advanced, non-destructive, in-line metrology solutions. These include techniques like optical critical dimension (OCD) scatterometry, X-ray reflectivity (XRR), and even in-line Transmission Electron Microscopy (TEM) to build a full 3D profile of the device at various stages of production.10
The complexity also creates immense challenges for defect localization and failure analysis. A tiny physical defect buried deep within the 3D structure can cause a device to fail, but it may be impossible to detect with surface inspection tools.29 This necessitates a higher volume of time-consuming cross-sectional analysis and the development of new fault isolation techniques. To manage this complexity at scale, advanced fabs are increasingly reliant on AI and machine learning algorithms. These systems analyze vast streams of real-time data from sensors on the manufacturing tools to predict and correct for process drifts before they result in yield-killing defects.10
4.4 Gate Stack Deposition and Thermal Budgets
Once the channels are released and suspended, the final gate stack must be formed. This involves depositing the high-k gate dielectric and the metal gate electrode. To ensure perfect, uniform coverage on all four sides of the nanosheets, this process must use Atomic Layer Deposition (ALD), a technique that builds up material one atomic layer at a time.10 Any non-uniformity in the gate stack thickness would compromise the electrostatic control that is the core benefit of the GAA architecture.
The entire fabrication flow must also be managed within a very strict thermal budget. The fragile, suspended nanosheets are highly susceptible to deformation or damage from thermal stress.10 This requires a complete re-engineering of thermal processing steps. Rapid Thermal Processing (RTP) systems are being reconfigured with advanced features like zonal heating and localized annealing to process specific layers without subjecting the entire device to excessive temperatures.10
The profound complexity and sensitivity of these processes mean that the entire fabrication facility must be designed and operated as a single, integrated system. It is no longer sufficient to optimize individual tools in isolation. The successful implementation of GAA requires a holistic approach that encompasses everything from stricter cleanroom zoning and airflow management to prevent particulate contamination, to module-to-module isolation to avoid chemical cross-contamination, to intelligent scheduling of wafer transfers between process steps.10 In this sense, GAA is not just a new transistor technology; it is a force of systemic change in fab design and operation, where the entire factory becomes the tool.
Section 5: The Foundry Race to 2nm and Beyond
The transition to Gate-All-Around technology is not just a technical evolution; it is a high-stakes competitive battleground for the world’s leading semiconductor foundries. The immense cost and complexity of developing and deploying a GAA manufacturing process have created a strategic inflection point in the industry. The divergent strategies, timelines, and branded technologies of Samsung, TSMC, and Intel reflect their unique market positions and technological ambitions, setting the stage for a dramatic reshaping of the foundry landscape in the 2nm era and beyond.
5.1 Samsung Foundry: The First Mover’s Gamble
Samsung Foundry made a bold and aggressive strategic decision to be the world’s first chipmaker to introduce GAA technology into high-volume manufacturing.30 They initiated production at their 3nm process node in mid-2022, aiming to leapfrog their competitors and reclaim the technological leadership they held in previous eras.18
Samsung’s GAA implementation is a nanosheet-based architecture branded as Multi-Bridge-Channel FET (MBCFET™).21 A key feature Samsung promotes is the design flexibility of MBCFET™, which allows the channel width of the nanosheets to be adjusted. This enables customers to finely tune transistor characteristics to optimize the PPA balance for their specific application needs—a significant advantage over the quantized fin widths of FinFETs.18
However, this first-mover strategy has been fraught with risk. Industry reports indicated that the initial 3nm GAA process was plagued by technical complexity and significant challenges in achieving high yields.30 While this early entry provided Samsung with invaluable hands-on experience with the novel architecture, the initial yield struggles may have limited its adoption by major customers. This experience, however, is now being applied to their second-generation 2nm GAA process (SF2P), which promises substantial improvements in performance, power, and area.32 Samsung’s gamble is that the lessons learned from the difficult 3nm ramp will translate into a more mature and competitive 2nm offering, potentially allowing them to win back market share from key clients.
5.2 TSMC: The Calculated Successor
In stark contrast to Samsung’s approach, Taiwan Semiconductor Manufacturing Company (TSMC) adopted a more conservative and calculated strategy. As the incumbent market leader, TSMC chose to extend its highly mature and high-yielding FinFET technology for its entire 3nm process family (N3, N3E, N3P, etc.), thereby providing a stable and predictable platform for its largest customers, such as Apple.9
TSMC’s entry into the GAA era is slated for its 2nm node (N2), with mass production scheduled to begin in the latter half of 2025.7 Their N2 process will feature the company’s first-generation nanosheet transistor technology.34 By delaying its GAA transition, TSMC’s strategy appears to be focused on maximizing the return on its massive FinFET investment while allowing its competitor to bear the initial risks and learning curve of GAA manufacturing. The expectation is that this will enable a smoother, faster, and higher-yielding production ramp for their N2 node. Early indications suggest this strategy is succeeding, as TSMC has reported that customer demand and the number of new tape-outs for its N2 process are significantly stronger than they were for its 3nm and 5nm nodes at a similar stage of development.19
5.3 Intel Foundry: The Resurgent Innovator’s Leapfrog
After falling behind its rivals during the later stages of the FinFET era, Intel is pursuing an ambitious “leapfrog” strategy to reclaim its historical position of technology leadership. Intel’s GAA implementation is a nanosheet architecture branded as RibbonFET, which is set to debut on its Intel 18A process node (equivalent to a 1.8nm class).7
Critically, Intel’s strategy is not just to introduce RibbonFET, but to launch it in conjunction with another groundbreaking technology: backside power delivery, which it calls PowerVia. The simultaneous introduction of two fundamental architectural innovations is an exceptionally high-risk endeavor but offers a potentially massive reward. If successful, the combination of RibbonFET and PowerVia could provide Intel’s 18A process with a decisive PPA advantage over the initial GAA offerings from Samsung and TSMC, which are not expected to introduce backside power until later nodes.19 Intel has already demonstrated working silicon with RibbonFET transistors at extremely scaled gate lengths and has announced securing multiple high-profile customer design wins for its 18A technology, signaling growing confidence in its aggressive roadmap.23
| Feature | Samsung Foundry | TSMC | Intel Foundry |
| Branded GAA Technology Name | Multi-Bridge-Channel FET (MBCFET™) | Nanosheet Transistor | RibbonFET |
| Architectural Type | Nanosheet | Nanosheet | Nanosheet (Ribbon) |
| Debut Process Node | 3nm (SF3) | 2nm (N2) | 18A (1.8nm-class) |
| Stated Mass Production Target | 2022 (for 3nm) | 2H 2025 (for 2nm) | 2H 2025 (for 18A) |
| Key Differentiating Feature/Strategy | First-Mover: First to HVM with GAA to gain experience, accepting initial yield challenges. | Calculated Successor: Extended mature FinFET at 3nm to ensure stability, targeting a high-yield GAA ramp at 2nm. | Technology Leapfrog: Bundling GAA (RibbonFET) with backside power delivery (PowerVia) at 18A to reclaim leadership. |
The divergent paths taken by the three leading foundries highlight three distinct corporate philosophies shaped by their respective market positions. Samsung, as the persistent challenger, has adopted a high-risk, pioneer strategy to disrupt the status quo. TSMC, as the dominant incumbent, is employing a lower-risk, fast-follower strategy designed to protect its market share and ensure stability for its key partners. Intel, as the resurgent former leader, is pursuing a high-risk, technology-leapfrog strategy to overcome its prior deficit in a single, decisive move.
Ultimately, Samsung’s experience with its 3nm node demonstrates that being the first to announce production is of little value if yields are low and costs are prohibitive.30 The true winner of the GAA transition will not be determined by timelines alone, but by manufacturing excellence. The foundry that can first achieve high, stable, and cost-effective yields will be the one to secure the high-volume orders from fabless giants like Apple, NVIDIA, AMD, and Qualcomm. This shifts the competitive focus from marketing announcements to the grueling, operational reality of process control and defect management. TSMC’s decision to delay GAA can be interpreted as a strategic bet that its renowned manufacturing maturity will allow it to achieve superior yields more quickly than its rivals, even with a later start. The battle for the Angstrom era will be fought and won on the factory floor.
Section 6: The Horizon Beyond GAA: Charting the Path to the Angstrom Era
The Gate-All-Around architecture is a critical innovation that will power the next decade of advanced computing, but it is not the final step in the evolution of the transistor. As the semiconductor industry looks toward the 1nm node and beyond, researchers at leading institutions and foundries are already developing the next generation of device structures and materials needed to continue the trajectory of Moore’s Law. The path forward will likely involve a holistic combination of new transistor architectures, novel channel materials, and advanced system-level integration techniques.
6.1 The Vertical Frontier: Complementary FETs (CFETs)
The leading architectural candidate to succeed GAA is the Complementary FET (CFET), also known as a 3D Stacked FET.38 The CFET represents a truly revolutionary leap in density by fundamentally changing the layout of the basic CMOS inverter, the building block of all digital logic.
In all previous transistor generations, including GAA, the n-type (nMOS) and p-type (pMOS) transistors that form an inverter are placed side-by-side on the silicon substrate. The CFET architecture achieves a monumental density improvement by stacking the nMOS and pMOS devices vertically, one on top of the other.38 This approach effectively halves the footprint required for a logic cell, enabling a full density scaling node that would be impossible with a lateral layout. The CFET would likely maintain the gate-all-around structure for both the top and bottom devices, but its fabrication would represent a disruptive move from a 2D to a 3D circuit layout.16
While conceptually elegant, the manufacturing challenges of CFETs are immense. The process would require finding a way to fabricate the top transistor, including its source, drain, and gate, without damaging the already-completed transistor underneath. This includes incredibly complex etching and deposition steps.38 Due to this complexity, CFETs are not expected to enter high-volume manufacturing until beyond 2030, but they represent the most promising path on industry roadmaps for scaling into the next decade.38
6.2 Emerging Materials and Architectures
In parallel with the development of new 3D structures like CFET, there is intense research into new materials that could one day replace silicon as the channel material, as well as other novel device concepts.
- New Channel Materials: To further enhance carrier mobility and performance, researchers are exploring materials beyond silicon and SiGe. Two-dimensional (2D) materials, such as transition metal dichalcogenides (TMDs) like molybdenum disulfide ($MoS_2$), are promising candidates due to their atomic-scale thickness and excellent electrical properties.15 Other materials like Germanium (Ge) for p-type transistors and even Carbon Nanotubes (CNTs) are also under investigation.13
- Evolutionary Architectures: Several evolutionary device structures are being explored as potential intermediate steps between GAA and CFET. The Forksheet FET, for example, modifies the GAA structure by introducing a dielectric wall between adjacent n-type and p-type nanosheets, allowing for a tighter packing of transistors and a further reduction in cell area.39 Other concepts include Vertical Transport FETs (VFETs), which orient the channel and current flow perpendicular to the wafer surface, and more exotic device concepts based on quantum tunneling or negative capacitance effects.39
6.3 Synthesis and Outlook: A New Paradigm for Scaling
The transition from FinFET to Gate-All-Around is more than a simple change in transistor geometry; it marks a fundamental shift in the paradigm of semiconductor scaling. It signifies the era where progress is driven not just by lithography, but by the co-optimization of materials science, device architecture, and advanced process control. The GAA architecture successfully solves the electrostatic and parasitic limitations of the FinFET, providing a robust and flexible platform that will carry the industry through the 2nm node and beyond.
The future of scaling, however, will not be defined by a single silver bullet. The continuation of Moore’s Law into the Angstrom era will depend on a holistic and multi-faceted approach. This will require the successful integration of revolutionary new transistor architectures like CFETs, the introduction of novel channel materials beyond silicon, and the continued advancement of system-level integration paradigms like 3D chip stacking and chiplet-based designs. This combined methodology, known as System Technology Co-Optimization (STCO), where the system architecture, circuit design, and manufacturing technology are all developed in concert, will be the guiding principle for future innovation.39 The relentless pursuit of smaller, faster, and more power-efficient transistors continues, promising a future where the boundaries of computation are constantly being redefined.